Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version      : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
| Date              : Fri May 16 22:42:32 2025
| Host              : linux-139028 running 64-bit Debian GNU/Linux 12 (bookworm)
| Command           : report_timing_summary -max_paths 10 -report_unconstrained -file d_1_wrapper_timing_summary_routed.rpt -pb d_1_wrapper_timing_summary_routed.pb -rpx d_1_wrapper_timing_summary_routed.rpx -warn_on_violation
| Design            : d_1_wrapper
| Device            : xczu28dr-ffvg1517
| Speed File        : -2  PRODUCTION 1.30 05-03-2022
| Design State      : Routed
| Temperature Grade : E
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                                                                            Violations  
---------  --------  -----------------------------------------------------------------------------------------------------  ----------  
LUTAR-1    Warning   LUT drives async reset alert                                                                           66          
TIMING-9   Warning   Unknown CDC Logic                                                                                      1           
TIMING-10  Warning   Missing property on synchronizer                                                                       1           
TIMING-18  Warning   Missing input or output delay                                                                          8           
TIMING-24  Warning   Overridden Max delay datapath only                                                                     8           
TIMING-47  Warning   False path, asynchronous clock group or max delay datapath only constraint between synchronous clocks  2           
CLKC-40    Advisory  Substitute PLLE4 for MMCME4 check                                                                      1           
CLKC-56    Advisory  MMCME4 with global clock driver has no LOC                                                             2           
XDCB-6     Advisory  Timing constraint pointing to hierarchical pins                                                        1           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (2)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (2)
------------------------------
 There are 2 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (9)
-------------------------------
 There are 9 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
     -0.011       -0.011                      1               530608        0.010        0.000                      0               529906        0.000        0.000                       0                186623  


Timing constraints are not met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                                Waveform(ns)           Period(ns)      Frequency(MHz)
-----                                                                                                ------------           ----------      --------------
RFADC0_CLK                                                                                           {0.000 1.953}          3.906           256.016         
  clk_out1_d_1_clk_adc0_x2_0                                                                         {0.000 0.976}          1.953           512.033         
RFADC0_CLK_dummy                                                                                     {0.000 1.953}          3.906           256.016         
RFADC1_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC1_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC1_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFADC2_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC2_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC2_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC2_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC2_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC2_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC3_CLK_dummy                                                                                     {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFADC3_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFDAC0_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFDAC0_FABCLK0                                                                                       {0.000 5.000}          10.000          100.000         
RFDAC0_FABCLK1                                                                                       {0.000 5.000}          10.000          100.000         
RFDAC0_FABCLK2                                                                                       {0.000 5.000}          10.000          100.000         
RFDAC0_FABCLK3                                                                                       {0.000 5.000}          10.000          100.000         
RFDAC1_CLK                                                                                           {0.000 1.221}          2.441           409.668         
clk_pl_0                                                                                             {0.000 5.000}          10.000          100.000         
  clk_out1_d_1_clk_core_0                                                                            {0.000 2.500}          5.000           200.000         
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {0.000 25.000}         50.000          20.000          
sys_clk_ddr4_clk_p                                                                                   {0.000 1.667}          3.334           299.940         
  mmcm_clkout0                                                                                       {0.000 1.500}          3.001           333.267         
    pll_clk[0]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[0]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[1]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[1]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[2]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[2]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
  mmcm_clkout5                                                                                       {0.000 6.001}          12.002          83.317          
  mmcm_clkout6                                                                                       {0.000 3.001}          6.001           166.633         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                                    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                                    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
RFADC0_CLK                                                                                                 3.042        0.000                      0                   46        0.035        0.000                      0                   46        0.586        0.000                       0                    37  
  clk_out1_d_1_clk_adc0_x2_0                                                                               0.068        0.000                      0               134478        0.010        0.000                      0               134478        0.030        0.000                       0                 43282  
RFDAC1_CLK                                                                                                 0.095        0.000                      0                59888        0.010        0.000                      0                59888        0.420        0.000                       0                 23541  
clk_pl_0                                                                                                   1.867        0.000                      0               203438        0.010        0.000                      0               203438        2.000        0.000                       0                 71812  
  clk_out1_d_1_clk_core_0                                                                                  0.134        0.000                      0                10198        0.015        0.000                      0                10198        1.958        0.000                       0                  3617  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       14.014        0.000                      0                  992        0.026        0.000                      0                  992       24.468        0.000                       0                   479  
sys_clk_ddr4_clk_p                                                                                         1.761        0.000                      0                   23        0.050        0.000                      0                   23        0.500        0.000                       0                    19  
  mmcm_clkout0                                                                                            -0.011       -0.011                      1               109923        0.010        0.000                      0               109923        0.000        0.000                       0                 41414  
    pll_clk[0]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[0]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[1]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[1]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[2]                                                                                                                                                                                                                                         0.000        0.000                       0                     7  
      pll_clk[2]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    25  
  mmcm_clkout5                                                                                             8.333        0.000                      0                  827        0.026        0.000                      0                  827        5.469        0.000                       0                   570  
  mmcm_clkout6                                                                                             0.969        0.000                      0                 5636        0.028        0.000                      0                 5152        0.985        0.000                       0                  1722  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       11.556        0.000                      0                    8                                                                        
mmcm_clkout5                                                                                         mmcm_clkout0                                                                                               2.147        0.000                      0                   28                                                                        
mmcm_clkout6                                                                                         mmcm_clkout0                                                                                               1.078        0.000                      0                  129                                                                        
mmcm_clkout0                                                                                         pll_clk[0]_DIV                                                                                             0.407        0.000                      0                  352        0.620        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[1]_DIV                                                                                             0.478        0.000                      0                  352        0.511        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[2]_DIV                                                                                             0.691        0.000                      0                  216        0.567        0.000                      0                  216  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                              49.425        0.000                      0                    8                                                                        
mmcm_clkout0                                                                                         mmcm_clkout5                                                                                              11.507        0.000                      0                   10                                                                        
mmcm_clkout0                                                                                         mmcm_clkout6                                                                                               1.247        0.000                      0                   36        0.249        0.000                      0                    1  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           ----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           clk_out1_d_1_clk_adc0_x2_0                                                                                 0.636        0.000                      0                    4        0.229        0.000                      0                    4  
**async_default**                                                                                    clk_out1_d_1_clk_core_0                                                                              clk_out1_d_1_clk_core_0                                                                                    0.739        0.000                      0                 1825        0.099        0.000                      0                 1825  
**async_default**                                                                                    clk_pl_0                                                                                             clk_pl_0                                                                                                   6.678        0.000                      0                 1986        0.159        0.000                      0                 1986  
**async_default**                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       47.003        0.000                      0                  100        0.104        0.000                      0                  100  
**async_default**                                                                                    mmcm_clkout5                                                                                         mmcm_clkout5                                                                                              10.337        0.000                      0                  105        0.116        0.000                      0                  105  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               RFDAC1_CLK                                                                                                                                                                                                
(none)                                                                                                                                                                                                    RFADC0_CLK                                                                                           
(none)                                                                                                                                                                                                    RFDAC1_CLK                                                                                           
(none)                                                                                               RFDAC1_CLK                                                                                           RFDAC1_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           RFDAC1_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              RFDAC1_CLK                                                                                           
(none)                                                                                               clk_pl_0                                                                                             RFDAC1_CLK                                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               RFDAC1_CLK                                                                                           clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                               mmcm_clkout0                                                                                         clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               RFDAC1_CLK                                                                                           clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                               RFADC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC2_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC3_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              clk_pl_0                                                                                             
(none)                                                                                               clk_pl_0                                                                                             clk_pl_0                                                                                             
(none)                                                                                               mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                               RFDAC1_CLK                                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_out1_d_1_clk_adc0_x2_0                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_pl_0                                                                                             mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout5                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               sys_clk_ddr4_clk_p                                                                                   mmcm_clkout0                                                                                         
(none)                                                                                               dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               sys_clk_ddr4_clk_p                                                                                   mmcm_clkout6                                                                                         
(none)                                                                                               clk_pl_0                                                                                             sys_clk_ddr4_clk_p                                                                                   


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               clk_pl_0                                                                                                                                                                                                  
(none)                                                                                               mmcm_clkout0                                                                                                                                                                                              
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_adc0_x2_0                                                                           
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                                                                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                                                                                                                                    sys_clk_ddr4_clk_p                                                                                   


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  RFADC0_CLK
  To Clock:  RFADC0_CLK

Setup :            0  Failing Endpoints,  Worst Slack        3.042ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.035ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.586ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             3.042ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
                            (rising edge-triggered cell SRL16E clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.736ns  (logic 0.508ns (69.022%)  route 0.228ns (30.978%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.117ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.068ns = ( 6.974 - 3.906 ) 
    Source Clock Delay      (SCD):    3.560ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.033ns (routing 1.852ns, distribution 1.181ns)
  Clock Net Delay (Destination): 2.682ns (routing 1.682ns, distribution 1.000ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          3.033     3.560    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X48Y258        SRL16E                                       r  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y258        SRL16E (Prop_H6LUT_SLICEM_CLK_Q)
                                                      0.392     3.952 r  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/Q
                         net (fo=1, routed)           0.210     4.162    d_1_i/rst_adc0/U0/EXT_LPF/Q
    SLICE_X51Y258        LUT3 (Prop_B5LUT_SLICEL_I2_O)
                                                      0.116     4.278 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.018     4.296    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0__0
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.682     6.974    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                         clock pessimism              0.375     7.349    
                         clock uncertainty           -0.035     7.313    
    SLICE_X51Y258        FDRE (Setup_BFF2_SLICEL_C_D)
                                                      0.025     7.338    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg
  -------------------------------------------------------------------
                         required time                          7.338    
                         arrival time                          -4.296    
  -------------------------------------------------------------------
                         slack                                  3.042    

Slack (MET) :             3.201ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/pr_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.575ns  (logic 0.081ns (14.086%)  route 0.494ns (85.914%))
  Logic Levels:           0  
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.023ns = ( 6.929 - 3.906 ) 
    Source Clock Delay      (SCD):    3.518ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.991ns (routing 1.852ns, distribution 1.139ns)
  Clock Net Delay (Destination): 2.637ns (routing 1.682ns, distribution 0.955ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.991     3.518    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y256        FDSE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     3.599 r  d_1_i/rst_adc0/U0/SEQ/pr_reg/Q
                         net (fo=2, routed)           0.494     4.093    d_1_i/rst_adc0/U0/Pr_out
    SLICE_X56Y270        FDRE                                         r  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.637     6.929    d_1_i/rst_adc0/U0/slowest_sync_clk
    SLICE_X56Y270        FDRE                                         r  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
                         clock pessimism              0.375     7.304    
                         clock uncertainty           -0.035     7.269    
    SLICE_X56Y270        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025     7.294    d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER
  -------------------------------------------------------------------
                         required time                          7.294    
                         arrival time                          -4.093    
  -------------------------------------------------------------------
                         slack                                  3.201    

Slack (MET) :             3.235ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.591ns  (logic 0.201ns (34.036%)  route 0.390ns (65.964%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -0.070ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.068ns = ( 6.974 - 3.906 ) 
    Source Clock Delay      (SCD):    3.513ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.986ns (routing 1.852ns, distribution 1.134ns)
  Clock Net Delay (Destination): 2.682ns (routing 1.682ns, distribution 1.000ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.986     3.513    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X52Y256        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y256        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.592 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q
                         net (fo=2, routed)           0.341     3.933    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/scndry_out
    SLICE_X51Y258        LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.122     4.055 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/lpf_exr_i_1/O
                         net (fo=1, routed)           0.049     4.104    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT_n_0
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.682     6.974    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
                         clock pessimism              0.375     7.349    
                         clock uncertainty           -0.035     7.314    
    SLICE_X51Y258        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     7.339    d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg
  -------------------------------------------------------------------
                         required time                          7.339    
                         arrival time                          -4.104    
  -------------------------------------------------------------------
                         slack                                  3.235    

Slack (MET) :             3.322ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/Core_reg/S
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.384ns  (logic 0.080ns (20.833%)  route 0.304ns (79.167%))
  Logic Levels:           0  
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.059ns = ( 6.965 - 3.906 ) 
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.998ns (routing 1.852ns, distribution 1.146ns)
  Clock Net Delay (Destination): 2.673ns (routing 1.682ns, distribution 0.991ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.998     3.525    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y258        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.605 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.304     3.909    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/S
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.673     6.965    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/C
                         clock pessimism              0.375     7.340    
                         clock uncertainty           -0.035     7.305    
    SLICE_X52Y256        FDSE (Setup_HFF_SLICEL_C_S)
                                                     -0.074     7.231    d_1_i/rst_adc0/U0/SEQ/Core_reg
  -------------------------------------------------------------------
                         required time                          7.231    
                         arrival time                          -3.909    
  -------------------------------------------------------------------
                         slack                                  3.322    

Slack (MET) :             3.322ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/from_sys_reg/S
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.384ns  (logic 0.080ns (20.833%)  route 0.304ns (79.167%))
  Logic Levels:           0  
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.059ns = ( 6.965 - 3.906 ) 
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.998ns (routing 1.852ns, distribution 1.146ns)
  Clock Net Delay (Destination): 2.673ns (routing 1.682ns, distribution 0.991ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.998     3.525    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y258        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.605 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.304     3.909    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/S
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.673     6.965    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                         clock pessimism              0.375     7.340    
                         clock uncertainty           -0.035     7.305    
    SLICE_X52Y256        FDSE (Setup_HFF2_SLICEL_C_S)
                                                     -0.074     7.231    d_1_i/rst_adc0/U0/SEQ/from_sys_reg
  -------------------------------------------------------------------
                         required time                          7.231    
                         arrival time                          -3.909    
  -------------------------------------------------------------------
                         slack                                  3.322    

Slack (MET) :             3.322ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/pr_reg/S
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.384ns  (logic 0.080ns (20.833%)  route 0.304ns (79.167%))
  Logic Levels:           0  
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.059ns = ( 6.965 - 3.906 ) 
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.998ns (routing 1.852ns, distribution 1.146ns)
  Clock Net Delay (Destination): 2.673ns (routing 1.682ns, distribution 0.991ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.998     3.525    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y258        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.605 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.304     3.909    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_reg/S
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.673     6.965    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/pr_reg/C
                         clock pessimism              0.375     7.340    
                         clock uncertainty           -0.035     7.305    
    SLICE_X52Y256        FDSE (Setup_GFF2_SLICEL_C_S)
                                                     -0.074     7.231    d_1_i/rst_adc0/U0/SEQ/pr_reg
  -------------------------------------------------------------------
                         required time                          7.231    
                         arrival time                          -3.909    
  -------------------------------------------------------------------
                         slack                                  3.322    

Slack (MET) :             3.322ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/R
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.384ns  (logic 0.080ns (20.833%)  route 0.304ns (79.167%))
  Logic Levels:           0  
  Clock Path Skew:        -0.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.059ns = ( 6.965 - 3.906 ) 
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.998ns (routing 1.852ns, distribution 1.146ns)
  Clock Net Delay (Destination): 2.673ns (routing 1.682ns, distribution 0.991ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.998     3.525    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y258        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     3.605 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/Q
                         net (fo=4, routed)           0.304     3.909    d_1_i/rst_adc0/U0/SEQ/lpf_int
    SLICE_X52Y256        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.673     6.965    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/seq_clr_reg/C
                         clock pessimism              0.375     7.340    
                         clock uncertainty           -0.035     7.305    
    SLICE_X52Y256        FDRE (Setup_EFF_SLICEL_C_R)
                                                     -0.074     7.231    d_1_i/rst_adc0/U0/SEQ/seq_clr_reg
  -------------------------------------------------------------------
                         required time                          7.231    
                         arrival time                          -3.909    
  -------------------------------------------------------------------
                         slack                                  3.322    

Slack (MET) :             3.338ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.549ns  (logic 0.230ns (41.890%)  route 0.319ns (58.110%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.060ns = ( 6.966 - 3.906 ) 
    Source Clock Delay      (SCD):    3.519ns
    Clock Pessimism Removal (CPR):    0.450ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.992ns (routing 1.852ns, distribution 1.140ns)
  Clock Net Delay (Destination): 2.674ns (routing 1.682ns, distribution 0.992ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.992     3.519    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y255        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     3.600 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/Q
                         net (fo=7, routed)           0.271     3.871    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[0]
    SLICE_X52Y255        LUT4 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     4.020 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[3]_i_1/O
                         net (fo=1, routed)           0.048     4.068    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[3]
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.674     6.966    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                         clock pessimism              0.450     7.416    
                         clock uncertainty           -0.035     7.381    
    SLICE_X52Y255        FDRE (Setup_GFF_SLICEL_C_D)
                                                      0.025     7.406    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]
  -------------------------------------------------------------------
                         required time                          7.406    
                         arrival time                          -4.068    
  -------------------------------------------------------------------
                         slack                                  3.338    

Slack (MET) :             3.344ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.543ns  (logic 0.224ns (41.290%)  route 0.319ns (58.710%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.060ns = ( 6.966 - 3.906 ) 
    Source Clock Delay      (SCD):    3.519ns
    Clock Pessimism Removal (CPR):    0.450ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.992ns (routing 1.852ns, distribution 1.140ns)
  Clock Net Delay (Destination): 2.674ns (routing 1.682ns, distribution 0.992ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.992     3.519    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y255        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     3.600 f  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/Q
                         net (fo=7, routed)           0.300     3.900    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[0]
    SLICE_X52Y255        LUT1 (Prop_F5LUT_SLICEL_I0_O)
                                                      0.143     4.043 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[0]_i_1/O
                         net (fo=1, routed)           0.019     4.062    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[0]
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.674     6.966    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]/C
                         clock pessimism              0.450     7.416    
                         clock uncertainty           -0.035     7.381    
    SLICE_X52Y255        FDRE (Setup_FFF2_SLICEL_C_D)
                                                      0.025     7.406    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[0]
  -------------------------------------------------------------------
                         required time                          7.406    
                         arrival time                          -4.062    
  -------------------------------------------------------------------
                         slack                                  3.344    

Slack (MET) :             3.351ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.906ns  (RFADC0_CLK rise@3.906ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.477ns  (logic 0.079ns (16.578%)  route 0.398ns (83.422%))
  Logic Levels:           0  
  Clock Path Skew:        -0.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.070ns = ( 6.976 - 3.906 ) 
    Source Clock Delay      (SCD):    3.513ns
    Clock Pessimism Removal (CPR):    0.375ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.986ns (routing 1.852ns, distribution 1.134ns)
  Clock Net Delay (Destination): 2.684ns (routing 1.682ns, distribution 1.002ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.986     3.513    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X52Y256        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y256        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.592 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q
                         net (fo=2, routed)           0.398     3.990    d_1_i/rst_adc0/U0/EXT_LPF/p_3_in6_in
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      3.906     3.906 r  
    HSADC_X0Y0           HSADC                        0.000     3.906 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     4.028 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     4.178    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     4.292 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.684     6.976    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
                         clock pessimism              0.375     7.351    
                         clock uncertainty           -0.035     7.316    
    SLICE_X51Y258        FDRE (Setup_FFF2_SLICEL_C_D)
                                                      0.025     7.341    d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]
  -------------------------------------------------------------------
                         required time                          7.341    
                         arrival time                          -3.990    
  -------------------------------------------------------------------
                         slack                                  3.351    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/Core_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/from_sys_reg/D
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.088ns  (logic 0.059ns (67.045%)  route 0.029ns (32.955%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.197ns
    Source Clock Delay      (SCD):    1.905ns
    Clock Pessimism Removal (CPR):    0.287ns
  Clock Net Delay (Source):      1.642ns (routing 1.008ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.845ns (routing 1.125ns, distribution 0.720ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.642     1.905    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y256        FDSE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/rst_adc0/U0/SEQ/Core_reg/Q
                         net (fo=2, routed)           0.023     1.967    d_1_i/rst_adc0/U0/SEQ/MB_out
    SLICE_X52Y256        LUT2 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.020     1.987 r  d_1_i/rst_adc0/U0/SEQ/from_sys_i_1/O
                         net (fo=1, routed)           0.006     1.993    d_1_i/rst_adc0/U0/SEQ/from_sys_i_1_n_0
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.845     2.197    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/from_sys_reg/C
                         clock pessimism             -0.287     1.911    
    SLICE_X52Y256        FDSE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.958    d_1_i/rst_adc0/U0/SEQ/from_sys_reg
  -------------------------------------------------------------------
                         required time                         -1.958    
                         arrival time                           1.993    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.060ns (65.325%)  route 0.032ns (34.675%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.199ns
    Source Clock Delay      (SCD):    1.908ns
    Clock Pessimism Removal (CPR):    0.286ns
  Clock Net Delay (Source):      1.645ns (routing 1.008ns, distribution 0.637ns)
  Clock Net Delay (Destination): 1.847ns (routing 1.125ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.645     1.908    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y258        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.947 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/Q
                         net (fo=2, routed)           0.025     1.971    d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr
    SLICE_X51Y258        LUT3 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.021     1.992 r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.007     1.999    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int0__0
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.847     2.199    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg/C
                         clock pessimism             -0.286     1.914    
    SLICE_X51Y258        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.961    d_1_i/rst_adc0/U0/EXT_LPF/lpf_int_reg
  -------------------------------------------------------------------
                         required time                         -1.961    
                         arrival time                           1.999    
  -------------------------------------------------------------------
                         slack                                  0.039    

Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.094ns  (logic 0.059ns (63.072%)  route 0.035ns (36.928%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.198ns
    Source Clock Delay      (SCD):    1.905ns
    Clock Pessimism Removal (CPR):    0.288ns
  Clock Net Delay (Source):      1.642ns (routing 1.008ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.846ns (routing 1.125ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.642     1.905    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y255        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.029     1.972    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X52Y255        LUT3 (Prop_H5LUT_SLICEL_I1_O)
                                                      0.020     1.992 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[2]_i_1/O
                         net (fo=1, routed)           0.006     1.998    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[2]
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.846     2.198    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]/C
                         clock pessimism             -0.288     1.911    
    SLICE_X52Y255        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.958    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.958    
                         arrival time                           1.998    
  -------------------------------------------------------------------
                         slack                                  0.041    

Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.094ns  (logic 0.059ns (63.072%)  route 0.035ns (36.928%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.198ns
    Source Clock Delay      (SCD):    1.905ns
    Clock Pessimism Removal (CPR):    0.288ns
  Clock Net Delay (Source):      1.642ns (routing 1.008ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.846ns (routing 1.125ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.642     1.905    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y255        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.029     1.972    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X52Y255        LUT5 (Prop_G5LUT_SLICEL_I2_O)
                                                      0.020     1.992 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[4]_i_1/O
                         net (fo=1, routed)           0.006     1.998    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[4]
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.846     2.198    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]/C
                         clock pessimism             -0.288     1.911    
    SLICE_X52Y255        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.047     1.958    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.958    
                         arrival time                           1.998    
  -------------------------------------------------------------------
                         slack                                  0.041    

Slack (MET) :             0.049ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.061ns (58.833%)  route 0.043ns (41.167%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.009ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.199ns
    Source Clock Delay      (SCD):    1.911ns
    Clock Pessimism Removal (CPR):    0.280ns
  Clock Net Delay (Source):      1.648ns (routing 1.008ns, distribution 0.640ns)
  Clock Net Delay (Destination): 1.847ns (routing 1.125ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.648     1.911    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y258        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.950 r  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/Q
                         net (fo=2, routed)           0.027     1.976    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/p_1_in4_in
    SLICE_X51Y258        LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.022     1.998 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/lpf_exr_i_1/O
                         net (fo=1, routed)           0.016     2.014    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT_n_0
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.847     2.199    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg/C
                         clock pessimism             -0.280     1.919    
    SLICE_X51Y258        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.046     1.965    d_1_i/rst_adc0/U0/EXT_LPF/lpf_exr_reg
  -------------------------------------------------------------------
                         required time                         -1.965    
                         arrival time                           2.014    
  -------------------------------------------------------------------
                         slack                                  0.049    

Slack (MET) :             0.050ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/Core_reg/C
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/Core_reg/D
                            (rising edge-triggered cell FDSE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.102ns  (logic 0.062ns (60.784%)  route 0.040ns (39.216%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.197ns
    Source Clock Delay      (SCD):    1.905ns
    Clock Pessimism Removal (CPR):    0.287ns
  Clock Net Delay (Source):      1.642ns (routing 1.008ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.845ns (routing 1.125ns, distribution 0.720ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.642     1.905    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y256        FDSE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/rst_adc0/U0/SEQ/Core_reg/Q
                         net (fo=2, routed)           0.023     1.967    d_1_i/rst_adc0/U0/SEQ/MB_out
    SLICE_X52Y256        LUT2 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.023     1.990 r  d_1_i/rst_adc0/U0/SEQ/Core_i_1/O
                         net (fo=1, routed)           0.017     2.007    d_1_i/rst_adc0/U0/SEQ/Core_i_1_n_0
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.845     2.197    d_1_i/rst_adc0/U0/SEQ/slowest_sync_clk
    SLICE_X52Y256        FDSE                                         r  d_1_i/rst_adc0/U0/SEQ/Core_reg/C
                         clock pessimism             -0.287     1.911    
    SLICE_X52Y256        FDSE (Hold_HFF_SLICEL_C_D)
                                                      0.046     1.957    d_1_i/rst_adc0/U0/SEQ/Core_reg
  -------------------------------------------------------------------
                         required time                         -1.957    
                         arrival time                           2.007    
  -------------------------------------------------------------------
                         slack                                  0.050    

Slack (MET) :             0.051ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.199ns
    Source Clock Delay      (SCD):    1.908ns
    Clock Pessimism Removal (CPR):    0.286ns
  Clock Net Delay (Source):      1.645ns (routing 1.008ns, distribution 0.637ns)
  Clock Net Delay (Destination): 1.847ns (routing 1.125ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.645     1.908    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y258        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.947 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3/Q
                         net (fo=1, routed)           0.064     2.011    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.s_level_out_d3
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.847     2.199    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                         clock pessimism             -0.286     1.914    
    SLICE_X51Y258        FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.046     1.960    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
  -------------------------------------------------------------------
                         required time                         -1.960    
                         arrival time                           2.011    
  -------------------------------------------------------------------
                         slack                                  0.051    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/lpf_asr_reg/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.072ns (68.779%)  route 0.033ns (31.221%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.199ns
    Source Clock Delay      (SCD):    1.908ns
    Clock Pessimism Removal (CPR):    0.286ns
  Clock Net Delay (Source):      1.645ns (routing 1.008ns, distribution 0.637ns)
  Clock Net Delay (Destination): 1.847ns (routing 1.125ns, distribution 0.722ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.645     1.908    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y258        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.947 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4/Q
                         net (fo=2, routed)           0.027     1.973    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/scndry_out
    SLICE_X51Y258        LUT5 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.033     2.006 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/lpf_asr_i_1/O
                         net (fo=1, routed)           0.006     2.012    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX_n_0
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_asr_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.847     2.199    d_1_i/rst_adc0/U0/EXT_LPF/slowest_sync_clk
    SLICE_X51Y258        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/lpf_asr_reg/C
                         clock pessimism             -0.286     1.914    
    SLICE_X51Y258        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.047     1.961    d_1_i/rst_adc0/U0/EXT_LPF/lpf_asr_reg
  -------------------------------------------------------------------
                         required time                         -1.961    
                         arrival time                           2.012    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.054ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.106ns  (logic 0.061ns (57.796%)  route 0.045ns (42.204%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.198ns
    Source Clock Delay      (SCD):    1.905ns
    Clock Pessimism Removal (CPR):    0.288ns
  Clock Net Delay (Source):      1.642ns (routing 1.008ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.846ns (routing 1.125ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.642     1.905    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y255        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.029     1.972    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X52Y255        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.994 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[3]_i_1/O
                         net (fo=1, routed)           0.016     2.010    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[3]
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.846     2.198    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]/C
                         clock pessimism             -0.288     1.911    
    SLICE_X52Y255        FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.046     1.957    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.957    
                         arrival time                           2.010    
  -------------------------------------------------------------------
                         slack                                  0.054    

Slack (MET) :             0.056ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             RFADC0_CLK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (RFADC0_CLK rise@0.000ns - RFADC0_CLK rise@0.000ns)
  Data Path Delay:        0.108ns  (logic 0.062ns (57.651%)  route 0.046ns (42.349%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.198ns
    Source Clock Delay      (SCD):    1.905ns
    Clock Pessimism Removal (CPR):    0.288ns
  Clock Net Delay (Source):      1.642ns (routing 1.008ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.846ns (routing 1.125ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.642     1.905    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y255        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.944 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/Q
                         net (fo=6, routed)           0.029     1.972    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/Q[1]
    SLICE_X52Y255        LUT2 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.023     1.995 r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int[1]_i_1/O
                         net (fo=1, routed)           0.017     2.012    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int0[1]
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.846     2.198    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/slowest_sync_clk
    SLICE_X52Y255        FDRE                                         r  d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]/C
                         clock pessimism             -0.288     1.911    
    SLICE_X52Y255        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.046     1.957    d_1_i/rst_adc0/U0/SEQ/SEQ_COUNTER/q_int_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.957    
                         arrival time                           2.012    
  -------------------------------------------------------------------
                         slack                                  0.056    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFADC0_CLK
Waveform(ns):       { 0.000 1.953 }
Period(ns):         3.906
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     HSADC/CLK_ADC      n/a            1.923         3.906       1.983      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Min Period        n/a     BUFG_GT/I          n/a            1.290         3.906       2.616      BUFG_GT_X1Y23  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.906       2.835      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Min Period        n/a     SRL16E/CLK         n/a            1.064         3.906       2.842      SLICE_X48Y258  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X56Y270  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[2].asr_lpf_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[3].asr_lpf_reg[3]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[1].exr_lpf_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.906       3.356      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/EXT_LPF[2].exr_lpf_reg[2]/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.906       96.094     MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Fast    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
Low Pulse Width   Slow    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X48Y258  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Low Pulse Width   Fast    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X48Y258  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X56Y270  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X56Y270  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.367         1.953       0.586      MMCM_X0Y7      d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Fast    HSADC/CLK_ADC      n/a            0.800         1.953       1.153      HSADC_X0Y0     d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
High Pulse Width  Slow    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X48Y258  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
High Pulse Width  Fast    SRL16E/CLK         n/a            0.532         1.953       1.421      SLICE_X48Y258  d_1_i/rst_adc0/U0/EXT_LPF/POR_SRL_I/CLK
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X56Y270  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X56Y270  d_1_i/rst_adc0/U0/PR_OUT_DFF[0].FDRE_PER/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.953       1.678      SLICE_X51Y258  d_1_i/rst_adc0/U0/EXT_LPF/AUX_LPF[1].asr_lpf_reg[1]/C



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.068ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.068ns  (required time - arrival time)
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.551ns  (logic 0.419ns (27.006%)  route 1.132ns (72.994%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.307ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.689ns = ( 8.642 - 1.953 ) 
    Source Clock Delay      (SCD):    6.878ns
    Clock Pessimism Removal (CPR):    -0.118ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.300ns (routing 1.562ns, distribution 1.738ns)
  Clock Net Delay (Destination): 2.886ns (routing 1.417ns, distribution 1.469ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.300     6.802    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.076     6.878 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FABRIC_CLK0_DATA_ADC0[38])
                                                      0.367     7.245 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DATA_ADC0[38]
                         net (fo=2, routed)           1.073     8.318    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s_axis_tdata[38]
    SLICE_X109Y80        LUT4 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.052     8.370 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1[38]_i_1/O
                         net (fo=1, routed)           0.059     8.429    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/p_0_in[38]
    SLICE_X109Y80        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.886     8.642    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X109Y80        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]/C
                         clock pessimism             -0.118     8.524    
                         clock uncertainty           -0.051     8.473    
    SLICE_X109Y80        FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025     8.498    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[38]
  -------------------------------------------------------------------
                         required time                          8.498    
                         arrival time                          -8.429    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.074ns  (required time - arrival time)
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[115]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.544ns  (logic 0.413ns (26.748%)  route 1.131ns (73.252%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.309ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.687ns = ( 8.640 - 1.953 ) 
    Source Clock Delay      (SCD):    6.878ns
    Clock Pessimism Removal (CPR):    -0.118ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.300ns (routing 1.562ns, distribution 1.738ns)
  Clock Net Delay (Destination): 2.884ns (routing 1.417ns, distribution 1.467ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.300     6.802    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.076     6.878 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FABRIC_CLK0_DATA_ADC0[115])
                                                      0.361     7.239 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DATA_ADC0[115]
                         net (fo=2, routed)           1.072     8.311    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s_axis_tdata[115]
    SLICE_X109Y82        LUT4 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.052     8.363 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1[115]_i_1/O
                         net (fo=1, routed)           0.059     8.422    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/p_0_in[115]
    SLICE_X109Y82        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[115]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.884     8.640    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X109Y82        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[115]/C
                         clock pessimism             -0.118     8.522    
                         clock uncertainty           -0.051     8.471    
    SLICE_X109Y82        FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025     8.496    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[115]
  -------------------------------------------------------------------
                         required time                          8.496    
                         arrival time                          -8.422    
  -------------------------------------------------------------------
                         slack                                  0.074    

Slack (MET) :             0.075ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[10]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.763ns  (logic 0.081ns (4.595%)  route 1.682ns (95.404%))
  Logic Levels:           0  
  Clock Path Skew:        -0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.683ns = ( 8.636 - 1.953 ) 
    Source Clock Delay      (SCD):    6.626ns
    Clock Pessimism Removal (CPR):    -0.061ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.124ns (routing 1.562ns, distribution 1.562ns)
  Clock Net Delay (Destination): 2.880ns (routing 1.417ns, distribution 1.463ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.124     6.626    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X88Y310        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y310        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     6.707 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/Q
                         net (fo=206, routed)         1.682     8.389    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/dds_tvalid_r_repN_13_alias
    SLICE_X99Y359        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[10]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.880     8.636    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/aclk
    SLICE_X99Y359        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[10]/C
                         clock pessimism             -0.061     8.575    
                         clock uncertainty           -0.051     8.524    
    SLICE_X99Y359        FDRE (Setup_AFF_SLICEM_C_CE)
                                                     -0.061     8.463    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[10]
  -------------------------------------------------------------------
                         required time                          8.463    
                         arrival time                          -8.389    
  -------------------------------------------------------------------
                         slack                                  0.075    

Slack (MET) :             0.075ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[10]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.763ns  (logic 0.081ns (4.595%)  route 1.682ns (95.404%))
  Logic Levels:           0  
  Clock Path Skew:        -0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.683ns = ( 8.636 - 1.953 ) 
    Source Clock Delay      (SCD):    6.626ns
    Clock Pessimism Removal (CPR):    -0.061ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.124ns (routing 1.562ns, distribution 1.562ns)
  Clock Net Delay (Destination): 2.880ns (routing 1.417ns, distribution 1.463ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.124     6.626    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X88Y310        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y310        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     6.707 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/Q
                         net (fo=206, routed)         1.682     8.389    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/dds_tvalid_r_repN_13_alias
    SLICE_X99Y359        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[10]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.880     8.636    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/aclk
    SLICE_X99Y359        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[10]/C
                         clock pessimism             -0.061     8.575    
                         clock uncertainty           -0.051     8.524    
    SLICE_X99Y359        FDRE (Setup_BFF_SLICEM_C_CE)
                                                     -0.061     8.463    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[10]
  -------------------------------------------------------------------
                         required time                          8.463    
                         arrival time                          -8.389    
  -------------------------------------------------------------------
                         slack                                  0.075    

Slack (MET) :             0.076ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[12]/CE
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.763ns  (logic 0.081ns (4.595%)  route 1.682ns (95.404%))
  Logic Levels:           0  
  Clock Path Skew:        -0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.683ns = ( 8.636 - 1.953 ) 
    Source Clock Delay      (SCD):    6.626ns
    Clock Pessimism Removal (CPR):    -0.061ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.124ns (routing 1.562ns, distribution 1.562ns)
  Clock Net Delay (Destination): 2.880ns (routing 1.417ns, distribution 1.463ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.124     6.626    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X88Y310        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y310        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     6.707 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_tvalid_r_reg_replica_13/Q
                         net (fo=206, routed)         1.682     8.389    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/dds_tvalid_r_repN_13_alias
    SLICE_X99Y359        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[12]/CE
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.880     8.636    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/aclk
    SLICE_X99Y359        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[12]/C
                         clock pessimism             -0.061     8.575    
                         clock uncertainty           -0.051     8.524    
    SLICE_X99Y359        FDRE (Setup_AFF2_SLICEM_C_CE)
                                                     -0.060     8.464    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[5].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[12]
  -------------------------------------------------------------------
                         required time                          8.464    
                         arrival time                          -8.389    
  -------------------------------------------------------------------
                         slack                                  0.076    

Slack (MET) :             0.078ns  (required time - arrival time)
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[64]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.553ns  (logic 0.505ns (32.525%)  route 1.048ns (67.475%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.700ns = ( 8.653 - 1.953 ) 
    Source Clock Delay      (SCD):    6.878ns
    Clock Pessimism Removal (CPR):    -0.118ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.300ns (routing 1.562ns, distribution 1.738ns)
  Clock Net Delay (Destination): 2.897ns (routing 1.417ns, distribution 1.480ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.300     6.802    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_INTERNAL_FABRIC_CLK0)
                                                      0.076     6.878 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FABRIC_CLK0
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FABRIC_CLK0_DATA_ADC0[64])
                                                      0.382     7.260 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DATA_ADC0[64]
                         net (fo=2, routed)           0.989     8.249    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s_axis_tdata[64]
    SLICE_X109Y71        LUT4 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.123     8.372 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1[64]_i_1/O
                         net (fo=1, routed)           0.059     8.431    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/p_0_in[64]
    SLICE_X109Y71        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[64]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.897     8.653    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X109Y71        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[64]/C
                         clock pessimism             -0.118     8.535    
                         clock uncertainty           -0.051     8.483    
    SLICE_X109Y71        FDRE (Setup_GFF_SLICEM_C_D)
                                                      0.025     8.508    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[64]
  -------------------------------------------------------------------
                         required time                          8.508    
                         arrival time                          -8.431    
  -------------------------------------------------------------------
                         slack                                  0.078    

Slack (MET) :             0.087ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][84]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[5].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][4]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.493ns  (logic 0.076ns (5.091%)  route 1.417ns (94.909%))
  Logic Levels:           0  
  Clock Path Skew:        -0.247ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.476ns = ( 8.429 - 1.953 ) 
    Source Clock Delay      (SCD):    6.567ns
    Clock Pessimism Removal (CPR):    -0.156ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.065ns (routing 1.562ns, distribution 1.503ns)
  Clock Net Delay (Destination): 2.673ns (routing 1.417ns, distribution 1.256ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.065     6.567    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/aclk
    SLICE_X87Y223        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][84]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y223        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     6.643 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.i_data_in/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][84]/Q
                         net (fo=2, routed)           1.417     8.060    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[5].i_data_casc_dly/data_in[4]
    SLICE_X69Y274        SRLC32E                                      r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[5].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][4]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.673     8.429    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[5].i_data_casc_dly/aclk
    SLICE_X69Y274        SRLC32E                                      r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[5].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][4]_srl32/CLK
                         clock pessimism             -0.156     8.273    
                         clock uncertainty           -0.051     8.222    
    SLICE_X69Y274        SRLC32E (Setup_D6LUT_SLICEM_CLK_D)
                                                     -0.075     8.147    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_array.g_data[5].i_data_casc_dly/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[31][4]_srl32
  -------------------------------------------------------------------
                         required time                          8.147    
                         arrival time                          -8.060    
  -------------------------------------------------------------------
                         slack                                  0.087    

Slack (MET) :             0.093ns  (required time - arrival time)
  Source:                 d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[25]_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.550ns  (logic 0.078ns (5.032%)  route 1.472ns (94.968%))
  Logic Levels:           0  
  Clock Path Skew:        -0.284ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.636ns = ( 8.589 - 1.953 ) 
    Source Clock Delay      (SCD):    6.785ns
    Clock Pessimism Removal (CPR):    -0.135ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.283ns (routing 1.562ns, distribution 1.721ns)
  Clock Net Delay (Destination): 2.833ns (routing 1.417ns, distribution 1.416ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.283     6.785    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X113Y55        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y55        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     6.863 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[25]/Q
                         net (fo=3, routed)           1.472     8.335    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s1_axis_tdata[25]_alias
    SLICE_X103Y166       FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[25]_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.833     8.589    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X103Y166       FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[25]_psdsp/C
                         clock pessimism             -0.135     8.454    
                         clock uncertainty           -0.051     8.403    
    SLICE_X103Y166       FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025     8.428    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[25]_psdsp
  -------------------------------------------------------------------
                         required time                          8.428    
                         arrival time                          -8.335    
  -------------------------------------------------------------------
                         slack                                  0.093    

Slack (MET) :             0.094ns  (required time - arrival time)
  Source:                 d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[43]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[43]_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.602ns  (logic 0.079ns (4.932%)  route 1.523ns (95.068%))
  Logic Levels:           0  
  Clock Path Skew:        -0.231ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.648ns = ( 8.601 - 1.953 ) 
    Source Clock Delay      (SCD):    6.744ns
    Clock Pessimism Removal (CPR):    -0.135ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.242ns (routing 1.562ns, distribution 1.680ns)
  Clock Net Delay (Destination): 2.845ns (routing 1.417ns, distribution 1.428ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.242     6.744    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X111Y67        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[43]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X111Y67        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     6.823 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[43]/Q
                         net (fo=3, routed)           1.523     8.346    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s1_axis_tdata[43]_alias
    SLICE_X100Y177       FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[43]_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.845     8.601    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X100Y177       FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[43]_psdsp/C
                         clock pessimism             -0.135     8.466    
                         clock uncertainty           -0.051     8.415    
    SLICE_X100Y177       FDRE (Setup_GFF_SLICEL_C_D)
                                                      0.025     8.440    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[43]_psdsp
  -------------------------------------------------------------------
                         required time                          8.440    
                         arrival time                          -8.346    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.095ns  (required time - arrival time)
  Source:                 d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[103]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[103]_psdsp/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.587ns  (logic 0.078ns (4.916%)  route 1.509ns (95.084%))
  Logic Levels:           0  
  Clock Path Skew:        -0.245ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.633ns = ( 8.586 - 1.953 ) 
    Source Clock Delay      (SCD):    6.726ns
    Clock Pessimism Removal (CPR):    -0.152ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.224ns (routing 1.562ns, distribution 1.662ns)
  Clock Net Delay (Destination): 2.830ns (routing 1.417ns, distribution 1.413ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.224     6.726    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X109Y68        FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[103]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y68        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     6.804 r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[103]/Q
                         net (fo=3, routed)           1.509     8.313    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/s1_axis_tdata[103]_alias
    SLICE_X101Y184       FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[103]_psdsp/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.830     8.586    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/aclk
    SLICE_X101Y184       FDRE                                         r  d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[103]_psdsp/C
                         clock pessimism             -0.152     8.434    
                         clock uncertainty           -0.051     8.382    
    SLICE_X101Y184       FDRE (Setup_EFF2_SLICEL_C_D)
                                                      0.025     8.407    d_1_i/axis_register_slice_0/inst/axisc_register_slice_0/storage_data1_reg[103]_psdsp
  -------------------------------------------------------------------
                         required time                          8.407    
                         arrival time                          -8.313    
  -------------------------------------------------------------------
                         slack                                  0.095    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.088ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.507ns
    Source Clock Delay      (SCD):    6.449ns
    Clock Pessimism Removal (CPR):    -0.030ns
  Clock Net Delay (Source):      2.646ns (routing 1.417ns, distribution 1.229ns)
  Clock Net Delay (Destination): 3.005ns (routing 1.562ns, distribution 1.443ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.646     6.449    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X70Y162        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y162        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.507 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     6.579    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_dly.i_data_sym_casc_dly/g_parallel.g_paths[5].data_sym_casc[57]_25[7]
    SLICE_X70Y163        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.005     6.507    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X70Y163        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.030     6.537    
    SLICE_X70Y163        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.569    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[51].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -6.569    
                         arrival time                           6.579    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[10].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.346ns  (logic 0.058ns (16.768%)  route 0.288ns (83.232%))
  Logic Levels:           0  
  Clock Path Skew:        0.304ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.569ns
    Source Clock Delay      (SCD):    6.420ns
    Clock Pessimism Removal (CPR):    -0.156ns
  Clock Net Delay (Source):      2.617ns (routing 1.417ns, distribution 1.200ns)
  Clock Net Delay (Destination): 3.067ns (routing 1.562ns, distribution 1.505ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.617     6.420    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[10].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X61Y236        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[10].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y236        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.478 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[10].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]/Q
                         net (fo=2, routed)           0.288     6.766    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/A[7]
    SLICE_X60Y254        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.067     6.569    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X60Y254        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7]_srl1/CLK
                         clock pessimism              0.156     6.725    
    SLICE_X60Y254        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.757    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[5].g_symmetric.g_data_sym_array.g_data_sym[9].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][7]_srl1
  -------------------------------------------------------------------
                         required time                         -6.757    
                         arrival time                           6.766    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.088ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.548ns
    Source Clock Delay      (SCD):    6.484ns
    Clock Pessimism Removal (CPR):    -0.024ns
  Clock Net Delay (Source):      2.681ns (routing 1.417ns, distribution 1.264ns)
  Clock Net Delay (Destination): 3.046ns (routing 1.562ns, distribution 1.484ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.681     6.484    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X54Y152        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y152        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.542 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[55].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     6.614    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X54Y153        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.046     6.548    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X54Y153        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.024     6.572    
    SLICE_X54Y153        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.604    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -6.604    
                         arrival time                           6.614    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[52].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.133ns  (logic 0.058ns (43.609%)  route 0.075ns (56.391%))
  Logic Levels:           0  
  Clock Path Skew:        0.091ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.515ns
    Source Clock Delay      (SCD):    6.455ns
    Clock Pessimism Removal (CPR):    -0.031ns
  Clock Net Delay (Source):      2.652ns (routing 1.417ns, distribution 1.235ns)
  Clock Net Delay (Destination): 3.013ns (routing 1.562ns, distribution 1.451ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.652     6.455    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[52].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X67Y173        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[52].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y173        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.513 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[52].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.075     6.588    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X67Y175        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.013     6.515    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X67Y175        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.031     6.546    
    SLICE_X67Y175        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.578    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[11].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -6.578    
                         arrival time                           6.588    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][13]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[13]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.333ns  (logic 0.060ns (18.018%)  route 0.273ns (81.982%))
  Logic Levels:           0  
  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.561ns
    Source Clock Delay      (SCD):    6.450ns
    Clock Pessimism Removal (CPR):    -0.156ns
  Clock Net Delay (Source):      2.647ns (routing 1.417ns, distribution 1.230ns)
  Clock Net Delay (Destination): 3.059ns (routing 1.562ns, distribution 1.497ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.647     6.450    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X75Y233        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y233        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.060     6.510 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][13]/Q
                         net (fo=1, routed)           0.273     6.783    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[13]
    SLICE_X75Y248        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[13]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.059     6.561    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X75Y248        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[13]_srl6/CLK
                         clock pessimism              0.156     6.717    
    SLICE_X75Y248        SRL16E (Hold_F5LUT_SLICEM_CLK_D)
                                                      0.056     6.773    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[13]_srl6
  -------------------------------------------------------------------
                         required time                         -6.773    
                         arrival time                           6.783    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[3].dds_dout_r2_reg[3][23]_srl2___inst_readout_top_i_down_conversion_fir_i_down_conversion_i_ctrl_i_outsel_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.127ns  (logic 0.061ns (47.915%)  route 0.066ns (52.085%))
  Logic Levels:           0  
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.763ns
    Source Clock Delay      (SCD):    6.676ns
    Clock Pessimism Removal (CPR):    0.003ns
  Clock Net Delay (Source):      2.873ns (routing 1.417ns, distribution 1.456ns)
  Clock Net Delay (Destination): 3.261ns (routing 1.562ns, distribution 1.699ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.873     6.676    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/aclk
    SLICE_X98Y248        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y248        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     6.737 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ls/opt_has_pipe.first_q_reg[7]/Q
                         net (fo=2, routed)           0.066     6.803    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_dout[3]_3[23]
    SLICE_X97Y248        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[3].dds_dout_r2_reg[3][23]_srl2___inst_readout_top_i_down_conversion_fir_i_down_conversion_i_ctrl_i_outsel_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.261     6.763    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X97Y248        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[3].dds_dout_r2_reg[3][23]_srl2___inst_readout_top_i_down_conversion_fir_i_down_conversion_i_ctrl_i_outsel_r2_reg_r/CLK
                         clock pessimism             -0.003     6.761    
    SLICE_X97Y248        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.793    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[3].dds_dout_r2_reg[3][23]_srl2___inst_readout_top_i_down_conversion_fir_i_down_conversion_i_ctrl_i_outsel_r2_reg_r
  -------------------------------------------------------------------
                         required time                         -6.793    
                         arrival time                           6.803    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.518ns
    Source Clock Delay      (SCD):    6.460ns
    Clock Pessimism Removal (CPR):    -0.028ns
  Clock Net Delay (Source):      2.657ns (routing 1.417ns, distribution 1.240ns)
  Clock Net Delay (Destination): 3.016ns (routing 1.562ns, distribution 1.454ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.657     6.460    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X76Y188        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y188        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.518 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     6.590    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X76Y189        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.016     6.518    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X76Y189        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.028     6.546    
    SLICE_X76Y189        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.578    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[0].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -6.578    
                         arrival time                           6.590    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[48].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.135ns  (logic 0.057ns (42.222%)  route 0.078ns (57.778%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.544ns
    Source Clock Delay      (SCD):    6.478ns
    Clock Pessimism Removal (CPR):    -0.029ns
  Clock Net Delay (Source):      2.675ns (routing 1.417ns, distribution 1.258ns)
  Clock Net Delay (Destination): 3.042ns (routing 1.562ns, distribution 1.480ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.675     6.478    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X76Y169        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y169        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     6.535 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[54].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/Q
                         net (fo=1, routed)           0.078     6.613    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[48].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]
    SLICE_X76Y168        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[48].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.042     6.544    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[48].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X76Y168        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[48].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/CLK
                         clock pessimism              0.029     6.573    
    SLICE_X76Y168        SRL16E (Hold_F6LUT_SLICEM_CLK_D)
                                                      0.029     6.602    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[48].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6
  -------------------------------------------------------------------
                         required time                         -6.602    
                         arrival time                           6.613    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[47].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.133ns  (logic 0.058ns (43.609%)  route 0.075ns (56.391%))
  Logic Levels:           0  
  Clock Path Skew:        0.089ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.565ns
    Source Clock Delay      (SCD):    6.499ns
    Clock Pessimism Removal (CPR):    -0.023ns
  Clock Net Delay (Source):      2.696ns (routing 1.417ns, distribution 1.279ns)
  Clock Net Delay (Destination): 3.063ns (routing 1.562ns, distribution 1.501ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.696     6.499    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X53Y159        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y159        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     6.557 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[53].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.075     6.632    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[47].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X53Y161        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[47].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.063     6.565    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[47].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X53Y161        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[47].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism              0.023     6.588    
    SLICE_X53Y161        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     6.620    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[47].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -6.620    
                         arrival time                           6.632    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             clk_out1_d_1_clk_adc0_x2_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.242ns  (logic 0.058ns (23.926%)  route 0.184ns (76.074%))
  Logic Levels:           0  
  Clock Path Skew:        0.202ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.558ns
    Source Clock Delay      (SCD):    6.508ns
    Clock Pessimism Removal (CPR):    -0.152ns
  Clock Net Delay (Source):      2.705ns (routing 1.417ns, distribution 1.288ns)
  Clock Net Delay (Destination): 3.056ns (routing 1.562ns, distribution 1.494ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.705     6.508    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X54Y175        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y175        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     6.566 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[1]/Q
                         net (fo=2, routed)           0.184     6.751    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/A[1]
    SLICE_X53Y183        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.056     6.558    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X53Y183        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1/CLK
                         clock pessimism              0.152     6.710    
    SLICE_X53Y183        SRL16E (Hold_B6LUT_SLICEM_CLK_D)
                                                      0.029     6.739    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[14].g_symmetric.g_data_sym_array.g_data_sym[38].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][1]_srl1
  -------------------------------------------------------------------
                         required time                         -6.739    
                         arrival time                           6.751    
  -------------------------------------------------------------------
                         slack                                  0.012    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_adc0_x2_0
Waveform(ns):       { 0.000 0.976 }
Period(ns):         1.953
Sources:            { d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     HSADC/FABRIC_CLK    n/a            1.923         1.953       0.030      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X3Y36  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X3Y37  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y40  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_12/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y41  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_13/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y42  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_14/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X4Y43  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         1.953       0.598      RAMB36_X7Y28  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_16/CLKARDCLK
Low Pulse Width   Slow    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Fast    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X3Y36  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X3Y36  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X3Y37  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X3Y37  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X4Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X4Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X4Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X4Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
High Pulse Width  Slow    HSADC/FABRIC_CLK    n/a            0.800         0.976       0.176      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Fast    HSADC/FABRIC_CLK    n/a            0.800         0.977       0.177      HSADC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X3Y36  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X3Y36  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X3Y37  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X3Y37  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X4Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X4Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         0.976       0.434      RAMB36_X4Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         0.977       0.435      RAMB36_X4Y39  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  RFDAC1_CLK
  To Clock:  RFDAC1_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.095ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.420ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.095ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[11]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.077ns  (logic 0.081ns (3.899%)  route 1.996ns (96.101%))
  Logic Levels:           0  
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.936ns = ( 5.377 - 2.441 ) 
    Source Clock Delay      (SCD):    3.397ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.724ns (routing 1.446ns, distribution 1.278ns)
  Clock Net Delay (Destination): 2.415ns (routing 1.313ns, distribution 1.102ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.724     3.397    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X33Y239        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y239        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     3.478 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/Q
                         net (fo=147, routed)         1.996     5.474    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/dds_tvalid_r_repN_20_alias
    SLICE_X37Y255        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[11]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.415     5.377    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/aclk
    SLICE_X37Y255        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[11]/C
                         clock pessimism              0.289     5.666    
                         clock uncertainty           -0.035     5.630    
    SLICE_X37Y255        FDRE (Setup_HFF2_SLICEM_C_CE)
                                                     -0.061     5.569    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[13].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[11]
  -------------------------------------------------------------------
                         required time                          5.569    
                         arrival time                          -5.474    
  -------------------------------------------------------------------
                         slack                                  0.095    

Slack (MET) :             0.095ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.077ns  (logic 0.081ns (3.899%)  route 1.996ns (96.101%))
  Logic Levels:           0  
  Clock Path Skew:        -0.172ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.936ns = ( 5.377 - 2.441 ) 
    Source Clock Delay      (SCD):    3.397ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.724ns (routing 1.446ns, distribution 1.278ns)
  Clock Net Delay (Destination): 2.415ns (routing 1.313ns, distribution 1.102ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.724     3.397    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X33Y239        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y239        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     3.478 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg_replica_20/Q
                         net (fo=147, routed)         1.996     5.474    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/dds_tvalid_r_repN_20_alias
    SLICE_X37Y255        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.415     5.377    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/aclk
    SLICE_X37Y255        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[0]/C
                         clock pessimism              0.289     5.666    
                         clock uncertainty           -0.035     5.630    
    SLICE_X37Y255        FDRE (Setup_GFF2_SLICEM_C_CE)
                                                     -0.061     5.569    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_b/opt_has_pipe.first_q_reg[0]
  -------------------------------------------------------------------
                         required time                          5.569    
                         arrival time                          -5.474    
  -------------------------------------------------------------------
                         slack                                  0.095    

Slack (MET) :             0.108ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[30]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.258ns  (logic 0.955ns (42.298%)  route 1.303ns (57.702%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.989ns = ( 5.430 - 2.441 ) 
    Source Clock Delay      (SCD):    3.333ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.660ns (routing 1.446ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.313ns, distribution 1.155ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.660     3.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X10Y107      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X10Y107      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.556 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[30]
                         net (fo=19, routed)          1.303     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[12]
    DSP48E2_X11Y72       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[12]_A_ALU[12])
                                                      0.194     5.053 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[12]
                         net (fo=1, routed)           0.000     5.053    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<12>
    DSP48E2_X11Y72       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[12]_ALU_OUT[30])
                                                      0.538     5.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[30]
                         net (fo=1, routed)           0.000     5.591    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<30>
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[30]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.468     5.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.289     5.719    
                         clock uncertainty           -0.035     5.684    
    DSP48E2_X11Y72       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[30])
                                                      0.015     5.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.699    
                         arrival time                          -5.591    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.108ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[31]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.258ns  (logic 0.955ns (42.298%)  route 1.303ns (57.702%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.989ns = ( 5.430 - 2.441 ) 
    Source Clock Delay      (SCD):    3.333ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.660ns (routing 1.446ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.313ns, distribution 1.155ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.660     3.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X10Y107      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X10Y107      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.556 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[30]
                         net (fo=19, routed)          1.303     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[12]
    DSP48E2_X11Y72       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[12]_A_ALU[12])
                                                      0.194     5.053 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[12]
                         net (fo=1, routed)           0.000     5.053    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<12>
    DSP48E2_X11Y72       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[12]_ALU_OUT[31])
                                                      0.538     5.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[31]
                         net (fo=1, routed)           0.000     5.591    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<31>
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[31]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.468     5.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.289     5.719    
                         clock uncertainty           -0.035     5.684    
    DSP48E2_X11Y72       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[31])
                                                      0.015     5.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.699    
                         arrival time                          -5.591    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.108ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[32]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.258ns  (logic 0.955ns (42.298%)  route 1.303ns (57.702%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.989ns = ( 5.430 - 2.441 ) 
    Source Clock Delay      (SCD):    3.333ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.660ns (routing 1.446ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.313ns, distribution 1.155ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.660     3.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X10Y107      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X10Y107      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.556 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[30]
                         net (fo=19, routed)          1.303     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[12]
    DSP48E2_X11Y72       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[12]_A_ALU[12])
                                                      0.194     5.053 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[12]
                         net (fo=1, routed)           0.000     5.053    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<12>
    DSP48E2_X11Y72       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[12]_ALU_OUT[32])
                                                      0.538     5.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[32]
                         net (fo=1, routed)           0.000     5.591    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<32>
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[32]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.468     5.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.289     5.719    
                         clock uncertainty           -0.035     5.684    
    DSP48E2_X11Y72       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[32])
                                                      0.015     5.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.699    
                         arrival time                          -5.591    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.108ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[33]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.258ns  (logic 0.955ns (42.298%)  route 1.303ns (57.702%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.989ns = ( 5.430 - 2.441 ) 
    Source Clock Delay      (SCD):    3.333ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.660ns (routing 1.446ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.313ns, distribution 1.155ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.660     3.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X10Y107      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X10Y107      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.556 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[30]
                         net (fo=19, routed)          1.303     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[12]
    DSP48E2_X11Y72       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[12]_A_ALU[12])
                                                      0.194     5.053 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[12]
                         net (fo=1, routed)           0.000     5.053    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<12>
    DSP48E2_X11Y72       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[12]_ALU_OUT[33])
                                                      0.538     5.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[33]
                         net (fo=1, routed)           0.000     5.591    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<33>
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[33]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.468     5.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.289     5.719    
                         clock uncertainty           -0.035     5.684    
    DSP48E2_X11Y72       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[33])
                                                      0.015     5.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.699    
                         arrival time                          -5.591    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.108ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[34]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.258ns  (logic 0.955ns (42.298%)  route 1.303ns (57.702%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.989ns = ( 5.430 - 2.441 ) 
    Source Clock Delay      (SCD):    3.333ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.660ns (routing 1.446ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.313ns, distribution 1.155ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.660     3.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X10Y107      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X10Y107      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.556 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[30]
                         net (fo=19, routed)          1.303     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[12]
    DSP48E2_X11Y72       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[12]_A_ALU[12])
                                                      0.194     5.053 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[12]
                         net (fo=1, routed)           0.000     5.053    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<12>
    DSP48E2_X11Y72       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[12]_ALU_OUT[34])
                                                      0.538     5.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[34]
                         net (fo=1, routed)           0.000     5.591    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<34>
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[34]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.468     5.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.289     5.719    
                         clock uncertainty           -0.035     5.684    
    DSP48E2_X11Y72       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[34])
                                                      0.015     5.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.699    
                         arrival time                          -5.591    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.108ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[35]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.258ns  (logic 0.955ns (42.298%)  route 1.303ns (57.702%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.989ns = ( 5.430 - 2.441 ) 
    Source Clock Delay      (SCD):    3.333ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.660ns (routing 1.446ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.313ns, distribution 1.155ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.660     3.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X10Y107      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X10Y107      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.556 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[30]
                         net (fo=19, routed)          1.303     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[12]
    DSP48E2_X11Y72       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[12]_A_ALU[12])
                                                      0.194     5.053 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[12]
                         net (fo=1, routed)           0.000     5.053    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<12>
    DSP48E2_X11Y72       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[12]_ALU_OUT[35])
                                                      0.538     5.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[35]
                         net (fo=1, routed)           0.000     5.591    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<35>
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[35]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.468     5.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.289     5.719    
                         clock uncertainty           -0.035     5.684    
    DSP48E2_X11Y72       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[35])
                                                      0.015     5.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.699    
                         arrival time                          -5.591    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.108ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[36]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.258ns  (logic 0.955ns (42.298%)  route 1.303ns (57.702%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.989ns = ( 5.430 - 2.441 ) 
    Source Clock Delay      (SCD):    3.333ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.660ns (routing 1.446ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.313ns, distribution 1.155ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.660     3.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X10Y107      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X10Y107      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.556 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[30]
                         net (fo=19, routed)          1.303     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[12]
    DSP48E2_X11Y72       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[12]_A_ALU[12])
                                                      0.194     5.053 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[12]
                         net (fo=1, routed)           0.000     5.053    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<12>
    DSP48E2_X11Y72       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[12]_ALU_OUT[36])
                                                      0.538     5.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[36]
                         net (fo=1, routed)           0.000     5.591    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<36>
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[36]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.468     5.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.289     5.719    
                         clock uncertainty           -0.035     5.684    
    DSP48E2_X11Y72       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[36])
                                                      0.015     5.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.699    
                         arrival time                          -5.591    
  -------------------------------------------------------------------
                         slack                                  0.108    

Slack (MET) :             0.108ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[37]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.441ns  (RFDAC1_CLK rise@2.441ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        2.258ns  (logic 0.955ns (42.298%)  route 1.303ns (57.702%))
  Logic Levels:           2  (DSP_A_B_DATA=1 DSP_ALU=1)
  Clock Path Skew:        -0.055ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.989ns = ( 5.430 - 2.441 ) 
    Source Clock Delay      (SCD):    3.333ns
    Clock Pessimism Removal (CPR):    0.289ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.660ns (routing 1.446ns, distribution 1.214ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.313ns, distribution 1.155ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.660     3.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X10Y107      DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X10Y107      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[30])
                                                      0.223     3.556 f  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QTIME_CTRL/TIME_ADDER/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/P[30]
                         net (fo=19, routed)          1.303     4.859    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/A[12]
    DSP48E2_X11Y72       DSP_A_B_DATA (Prop_DSP_A_B_DATA_DSP48E2_A[12]_A_ALU[12])
                                                      0.194     5.053 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA_INST/A_ALU[12]
                         net (fo=1, routed)           0.000     5.053    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_A_B_DATA.A_ALU<12>
    DSP48E2_X11Y72       DSP_ALU (Prop_DSP_ALU_DSP48E2_A_ALU[12]_ALU_OUT[37])
                                                      0.538     5.591 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[37]
                         net (fo=1, routed)           0.000     5.591    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<37>
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[37]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      2.441     2.441 r  
    HSDAC_X0Y1           HSDAC                        0.000     2.441 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.722 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     2.848    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.962 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.468     5.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X11Y72       DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.289     5.719    
                         clock uncertainty           -0.035     5.684    
    DSP48E2_X11Y72       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[37])
                                                      0.015     5.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.699    
                         arrival time                          -5.591    
  -------------------------------------------------------------------
                         slack                                  0.108    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r5_reg[4]_srl5___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r5_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.313ns  (logic 0.058ns (18.558%)  route 0.255ns (81.442%))
  Logic Levels:           0  
  Clock Path Skew:        0.277ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.495ns
    Source Clock Delay      (SCD):    2.933ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Net Delay (Source):      2.412ns (routing 1.313ns, distribution 1.099ns)
  Clock Net Delay (Destination): 2.822ns (routing 1.446ns, distribution 1.376ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.412     2.933    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X64Y296        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y296        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.991 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_reg[4]/Q
                         net (fo=4, routed)           0.255     3.246    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_reg[4]
    SLICE_X66Y303        SRL16E                                       r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r5_reg[4]_srl5___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r5_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.822     3.495    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X66Y303        SRL16E                                       r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r5_reg[4]_srl5___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r5_reg_r/CLK
                         clock pessimism             -0.285     3.210    
    SLICE_X66Y303        SRL16E (Hold_E6LUT_SLICEM_CLK_D)
                                                      0.026     3.236    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r5_reg[4]_srl5___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r5_reg_r
  -------------------------------------------------------------------
                         required time                         -3.236    
                         arrival time                           3.246    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1099]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.131ns  (logic 0.059ns (45.042%)  route 0.072ns (54.958%))
  Logic Levels:           0  
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.389ns
    Source Clock Delay      (SCD):    2.925ns
    Clock Pessimism Removal (CPR):    0.406ns
  Clock Net Delay (Source):      2.404ns (routing 1.313ns, distribution 1.091ns)
  Clock Net Delay (Destination): 2.716ns (routing 1.446ns, distribution 1.270ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.404     2.925    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X47Y364        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1099]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y364        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     2.984 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1099]/Q
                         net (fo=32, routed)          0.072     3.056    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/s_axis_phase_tdata[19]
    SLICE_X47Y363        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.716     3.389    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/aclk
    SLICE_X47Y363        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[19]/C
                         clock pessimism             -0.406     2.983    
    SLICE_X47Y363        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     3.045    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[15].dds_i/U0/i_synth/has_s_phase.i_has_no_tready.reg_s_phase_fifo_din_reg[19]
  -------------------------------------------------------------------
                         required time                         -3.045    
                         arrival time                           3.056    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][11]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][11]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.261ns  (logic 0.059ns (22.615%)  route 0.202ns (77.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.195ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.471ns
    Source Clock Delay      (SCD):    2.923ns
    Clock Pessimism Removal (CPR):    0.353ns
  Clock Net Delay (Source):      2.402ns (routing 1.313ns, distribution 1.089ns)
  Clock Net Delay (Destination): 2.798ns (routing 1.446ns, distribution 1.352ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.402     2.923    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/aclk
    SLICE_X59Y311        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y311        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     2.982 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][11]/Q
                         net (fo=2, routed)           0.202     3.183    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/B[11]
    SLICE_X63Y311        SRL16E                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][11]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.798     3.471    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/aclk
    SLICE_X63Y311        SRL16E                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][11]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/CLK
                         clock pessimism             -0.353     3.118    
    SLICE_X63Y311        SRL16E (Hold_D5LUT_SLICEM_CLK_D)
                                                      0.054     3.172    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][11]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r
  -------------------------------------------------------------------
                         required time                         -3.172    
                         arrival time                           3.183    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[10].phase_v1_r1_reg[10][5]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[757]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.059ns (31.892%)  route 0.126ns (68.108%))
  Logic Levels:           0  
  Clock Path Skew:        0.113ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.410ns
    Source Clock Delay      (SCD):    2.940ns
    Clock Pessimism Removal (CPR):    0.357ns
  Clock Net Delay (Source):      2.419ns (routing 1.313ns, distribution 1.106ns)
  Clock Net Delay (Destination): 2.737ns (routing 1.446ns, distribution 1.291ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.419     2.940    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X38Y369        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[10].phase_v1_r1_reg[10][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y369        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     2.999 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[10].phase_v1_r1_reg[10][5]/Q
                         net (fo=1, routed)           0.126     3.125    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[757]
    SLICE_X39Y369        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[757]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.737     3.410    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X39Y369        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[757]/C
                         clock pessimism             -0.357     3.053    
    SLICE_X39Y369        FDRE (Hold_AFF_SLICEM_C_D)
                                                      0.060     3.113    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[757]
  -------------------------------------------------------------------
                         required time                         -3.113    
                         arrival time                           3.125    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r5_reg[5]_srl5___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r5_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.318ns  (logic 0.058ns (18.260%)  route 0.260ns (81.740%))
  Logic Levels:           0  
  Clock Path Skew:        0.277ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.495ns
    Source Clock Delay      (SCD):    2.933ns
    Clock Pessimism Removal (CPR):    0.285ns
  Clock Net Delay (Source):      2.412ns (routing 1.313ns, distribution 1.099ns)
  Clock Net Delay (Destination): 2.822ns (routing 1.446ns, distribution 1.376ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.412     2.933    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X64Y296        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y296        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     2.991 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_reg[5]/Q
                         net (fo=3, routed)           0.260     3.251    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_reg[5]
    SLICE_X66Y303        SRL16E                                       r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r5_reg[5]_srl5___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r5_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.822     3.495    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X66Y303        SRL16E                                       r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r5_reg[5]_srl5___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r5_reg_r/CLK
                         clock pessimism             -0.285     3.210    
    SLICE_X66Y303        SRL16E (Hold_F6LUT_SLICEM_CLK_D)
                                                      0.029     3.239    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/addr_cnt_r5_reg[5]_srl5___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r5_reg_r
  -------------------------------------------------------------------
                         required time                         -3.239    
                         arrival time                           3.251    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[2].phase_v1_r1_reg[2][24]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[200]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.173ns  (logic 0.058ns (33.526%)  route 0.115ns (66.474%))
  Logic Levels:           0  
  Clock Path Skew:        0.101ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.400ns
    Source Clock Delay      (SCD):    2.942ns
    Clock Pessimism Removal (CPR):    0.357ns
  Clock Net Delay (Source):      2.421ns (routing 1.313ns, distribution 1.108ns)
  Clock Net Delay (Destination): 2.727ns (routing 1.446ns, distribution 1.281ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.421     2.942    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X41Y365        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[2].phase_v1_r1_reg[2][24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y365        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     3.000 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[2].phase_v1_r1_reg[2][24]/Q
                         net (fo=1, routed)           0.115     3.115    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[200]
    SLICE_X40Y366        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[200]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.727     3.400    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X40Y366        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[200]/C
                         clock pessimism             -0.357     3.043    
    SLICE_X40Y366        FDRE (Hold_BFF_SLICEL_C_D)
                                                      0.060     3.103    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[200]
  -------------------------------------------------------------------
                         required time                         -3.103    
                         arrival time                           3.115    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/i_large_lfsr.lfsr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/i_large_lfsr.lfsr_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.061ns (38.754%)  route 0.096ns (61.246%))
  Logic Levels:           0  
  Clock Path Skew:        0.082ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.351ns
    Source Clock Delay      (SCD):    2.919ns
    Clock Pessimism Removal (CPR):    0.350ns
  Clock Net Delay (Source):      2.398ns (routing 1.313ns, distribution 1.085ns)
  Clock Net Delay (Destination): 2.678ns (routing 1.446ns, distribution 1.232ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.398     2.919    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/CLK
    SLICE_X54Y359        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/i_large_lfsr.lfsr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y359        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     2.980 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/i_large_lfsr.lfsr_reg[4]/Q
                         net (fo=2, routed)           0.096     3.076    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/DITHER[3]
    SLICE_X53Y359        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/i_large_lfsr.lfsr_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.678     3.351    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/CLK
    SLICE_X53Y359        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/i_large_lfsr.lfsr_reg[14]/C
                         clock pessimism             -0.350     3.001    
    SLICE_X53Y359        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     3.063    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_dither.i_dither/i_large_lfsr.lfsr_reg[14]
  -------------------------------------------------------------------
                         required time                         -3.063    
                         arrival time                           3.076    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[13].phase_v1_r1_reg[13][21]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[989]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.057ns (33.728%)  route 0.112ns (66.272%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.393ns
    Source Clock Delay      (SCD):    2.942ns
    Clock Pessimism Removal (CPR):    0.357ns
  Clock Net Delay (Source):      2.421ns (routing 1.313ns, distribution 1.108ns)
  Clock Net Delay (Destination): 2.720ns (routing 1.446ns, distribution 1.274ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.421     2.942    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X41Y376        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[13].phase_v1_r1_reg[13][21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y376        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     2.999 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[13].phase_v1_r1_reg[13][21]/Q
                         net (fo=1, routed)           0.112     3.111    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[989]
    SLICE_X40Y377        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[989]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.720     3.393    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X40Y377        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[989]/C
                         clock pessimism             -0.357     3.036    
    SLICE_X40Y377        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     3.096    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[989]
  -------------------------------------------------------------------
                         required time                         -3.096    
                         arrival time                           3.111    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[14].phase_v0_r4_reg[14][3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[14].phase_v1_r1_reg[14][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.106ns (56.389%)  route 0.082ns (43.611%))
  Logic Levels:           2  (CARRY8=1 LUT2=1)
  Clock Path Skew:        0.113ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.404ns
    Source Clock Delay      (SCD):    2.934ns
    Clock Pessimism Removal (CPR):    0.357ns
  Clock Net Delay (Source):      2.413ns (routing 1.313ns, distribution 1.100ns)
  Clock Net Delay (Destination): 2.731ns (routing 1.446ns, distribution 1.285ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.413     2.934    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X56Y365        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[14].phase_v0_r4_reg[14][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y365        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     2.992 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[14].phase_v0_r4_reg[14][3]/Q
                         net (fo=2, routed)           0.062     3.054    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[14].phase_v0_r4_reg[14]_10[3]
    SLICE_X55Y365        LUT2 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.022     3.076 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[14]_carry_i_6/O
                         net (fo=1, routed)           0.010     3.086    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[14]_carry_i_6_n_0
    SLICE_X55Y365        CARRY8 (Prop_CARRY8_SLICEL_S[2]_O[2])
                                                      0.026     3.112 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[14]_carry/O[2]
                         net (fo=1, routed)           0.010     3.122    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[14]_79[3]
    SLICE_X55Y365        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[14].phase_v1_r1_reg[14][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.731     3.404    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X55Y365        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[14].phase_v1_r1_reg[14][3]/C
                         clock pessimism             -0.357     3.047    
    SLICE_X55Y365        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     3.107    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[14].phase_v1_r1_reg[14][3]
  -------------------------------------------------------------------
                         required time                         -3.107    
                         arrival time                           3.122    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             RFDAC1_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC1_CLK rise@0.000ns - RFDAC1_CLK rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.081ns (29.670%)  route 0.192ns (70.330%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.197ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.410ns
    Source Clock Delay      (SCD):    2.920ns
    Clock Pessimism Removal (CPR):    0.293ns
  Clock Net Delay (Source):      2.399ns (routing 1.313ns, distribution 1.086ns)
  Clock Net Delay (Destination): 2.737ns (routing 1.446ns, distribution 1.291ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.399     2.920    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/aclk
    SLICE_X39Y357        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y357        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     2.978 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_rom_reg_a/opt_has_pipe.first_q_reg[8]/Q
                         net (fo=1, routed)           0.162     3.140    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[6][0]
    SLICE_X39Y367        LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.023     3.163 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q[0]_i_1__1/O
                         net (fo=1, routed)           0.030     3.193    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/D[0]
    SLICE_X39Y367        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.737     3.410    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/aclk
    SLICE_X39Y367        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q_reg[0]/C
                         clock pessimism             -0.293     3.117    
    SLICE_X39Y367        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.060     3.177    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/GEN_dds[10].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_original_sin_ms/opt_has_pipe.first_q_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.177    
                         arrival time                           3.193    
  -------------------------------------------------------------------
                         slack                                  0.016    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFDAC1_CLK
Waveform(ns):       { 0.000 1.220 }
Period(ns):         2.441
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     HSDAC/CLK_DAC       n/a            2.000         2.441       0.441      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
Min Period        n/a     HSDAC/FABRIC_CLK    n/a            2.000         2.441       0.441      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X5Y72  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X6Y70  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X5Y67  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X5Y66  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X5Y75  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X7Y75  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X5Y74  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         2.441       1.086      RAMB36_X5Y73  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_1/CLKBWRCLK
Low Pulse Width   Slow    HSDAC/CLK_DAC       n/a            0.800         1.220       0.420      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
Low Pulse Width   Fast    HSDAC/CLK_DAC       n/a            0.800         1.220       0.420      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
Low Pulse Width   Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.220       0.420      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.220       0.420      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB36_X5Y72  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB36_X5Y72  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB36_X6Y70  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB36_X6Y70  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB36_X5Y67  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB36_X5Y67  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    HSDAC/CLK_DAC       n/a            0.800         1.221       0.421      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
High Pulse Width  Fast    HSDAC/CLK_DAC       n/a            0.800         1.221       0.421      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
High Pulse Width  Slow    HSDAC/FABRIC_CLK    n/a            0.800         1.221       0.421      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Fast    HSDAC/FABRIC_CLK    n/a            0.800         1.220       0.420      HSDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB36_X5Y72  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB36_X5Y72  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB36_X6Y70  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB36_X6Y70  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         1.221       0.679      RAMB36_X5Y67  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         1.220       0.678      RAMB36_X5Y67  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        1.867ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.867ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg40_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.820ns  (logic 0.668ns (8.543%)  route 7.152ns (91.457%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.209ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.154ns = ( 12.154 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 1.972ns (routing 0.703ns, distribution 1.269ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.519     8.591    d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X44Y103        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     8.690 r  d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=64, routed)          1.633    10.323    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X42Y130        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg40_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.972    12.154    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X42Y130        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg40_reg[6]/C
                         clock pessimism              0.140    12.294    
                         clock uncertainty           -0.130    12.165    
    SLICE_X42Y130        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.190    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg40_reg[6]
  -------------------------------------------------------------------
                         required time                         12.190    
                         arrival time                         -10.323    
  -------------------------------------------------------------------
                         slack                                  1.867    

Slack (MET) :             1.899ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.754ns  (logic 0.668ns (8.615%)  route 7.086ns (91.385%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.242ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.121ns = ( 12.121 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 1.939ns (routing 0.703ns, distribution 1.236ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.519     8.591    d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X44Y103        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     8.690 r  d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=64, routed)          1.567    10.257    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X42Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.939    12.121    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X42Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/C
                         clock pessimism              0.140    12.261    
                         clock uncertainty           -0.130    12.131    
    SLICE_X42Y148        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025    12.156    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]
  -------------------------------------------------------------------
                         required time                         12.156    
                         arrival time                         -10.257    
  -------------------------------------------------------------------
                         slack                                  1.899    

Slack (MET) :             1.907ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg8_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.769ns  (logic 0.668ns (8.598%)  route 7.101ns (91.402%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.220ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.143ns = ( 12.143 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 1.961ns (routing 0.703ns, distribution 1.258ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.519     8.591    d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X44Y103        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     8.690 r  d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=64, routed)          1.582    10.272    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X39Y147        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg8_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.961    12.143    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X39Y147        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg8_reg[6]/C
                         clock pessimism              0.140    12.283    
                         clock uncertainty           -0.130    12.154    
    SLICE_X39Y147        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025    12.179    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg8_reg[6]
  -------------------------------------------------------------------
                         required time                         12.179    
                         arrival time                         -10.272    
  -------------------------------------------------------------------
                         slack                                  1.907    

Slack (MET) :             1.969ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.685ns  (logic 0.668ns (8.692%)  route 7.017ns (91.308%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.241ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.122ns = ( 12.122 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 1.940ns (routing 0.703ns, distribution 1.237ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.519     8.591    d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X44Y103        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     8.690 r  d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=64, routed)          1.498    10.188    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.940    12.122    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/C
                         clock pessimism              0.140    12.262    
                         clock uncertainty           -0.130    12.132    
    SLICE_X38Y148        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    12.157    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]
  -------------------------------------------------------------------
                         required time                         12.157    
                         arrival time                         -10.188    
  -------------------------------------------------------------------
                         slack                                  1.969    

Slack (MET) :             1.976ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg0_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.685ns  (logic 0.668ns (8.693%)  route 7.017ns (91.307%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.235ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.128ns = ( 12.128 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.703ns, distribution 1.243ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.519     8.591    d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X44Y103        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     8.690 r  d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=64, routed)          1.498    10.188    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X41Y146        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg0_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.946    12.128    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X41Y146        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg0_reg[6]/C
                         clock pessimism              0.140    12.268    
                         clock uncertainty           -0.130    12.138    
    SLICE_X41Y146        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025    12.163    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg0_reg[6]
  -------------------------------------------------------------------
                         required time                         12.163    
                         arrival time                         -10.188    
  -------------------------------------------------------------------
                         slack                                  1.976    

Slack (MET) :             2.001ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg9_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.676ns  (logic 0.668ns (8.702%)  route 7.008ns (91.298%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.219ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.144ns = ( 12.144 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 1.962ns (routing 0.703ns, distribution 1.259ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.519     8.591    d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X44Y103        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     8.690 r  d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=64, routed)          1.489    10.179    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X39Y146        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg9_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.962    12.144    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X39Y146        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg9_reg[6]/C
                         clock pessimism              0.140    12.284    
                         clock uncertainty           -0.130    12.155    
    SLICE_X39Y146        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.180    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg9_reg[6]
  -------------------------------------------------------------------
                         required time                         12.180    
                         arrival time                         -10.179    
  -------------------------------------------------------------------
                         slack                                  2.001    

Slack (MET) :             2.007ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg9_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.696ns  (logic 0.622ns (8.082%)  route 7.074ns (91.918%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.189ns = ( 12.189 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 2.007ns (routing 0.703ns, distribution 1.304ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.145     8.217    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X75Y102        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.053     8.270 r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=16, routed)          1.929    10.199    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X72Y196        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg9_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.007    12.189    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X72Y196        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg9_reg[6]/C
                         clock pessimism              0.122    12.311    
                         clock uncertainty           -0.130    12.181    
    SLICE_X72Y196        FDRE (Setup_EFF2_SLICEM_C_D)
                                                      0.025    12.206    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg9_reg[6]
  -------------------------------------------------------------------
                         required time                         12.206    
                         arrival time                         -10.199    
  -------------------------------------------------------------------
                         slack                                  2.007    

Slack (MET) :             2.022ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.632ns  (logic 0.668ns (8.753%)  route 6.964ns (91.247%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.241ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.122ns = ( 12.122 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 1.940ns (routing 0.703ns, distribution 1.237ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.519     8.591    d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X44Y103        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     8.690 r  d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=64, routed)          1.445    10.135    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X43Y150        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.940    12.122    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X43Y150        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[6]/C
                         clock pessimism              0.140    12.262    
                         clock uncertainty           -0.130    12.132    
    SLICE_X43Y150        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025    12.157    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[6]
  -------------------------------------------------------------------
                         required time                         12.157    
                         arrival time                         -10.135    
  -------------------------------------------------------------------
                         slack                                  2.022    

Slack (MET) :             2.060ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg1_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.642ns  (logic 0.622ns (8.139%)  route 7.020ns (91.861%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.189ns = ( 12.189 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 2.007ns (routing 0.703ns, distribution 1.304ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.145     8.217    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X75Y102        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.053     8.270 r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=16, routed)          1.875    10.145    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X72Y201        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg1_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.007    12.189    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X72Y201        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg1_reg[6]/C
                         clock pessimism              0.122    12.311    
                         clock uncertainty           -0.130    12.181    
    SLICE_X72Y201        FDRE (Setup_FFF2_SLICEM_C_D)
                                                      0.025    12.206    d_1_i/axis_avg_buffer_0/inst/axi_slv_i/slv_reg1_reg[6]
  -------------------------------------------------------------------
                         required time                         12.206    
                         arrival time                         -10.145    
  -------------------------------------------------------------------
                         slack                                  2.060    

Slack (MET) :             2.079ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg15_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.595ns  (logic 0.668ns (8.795%)  route 6.927ns (91.205%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.222ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.141ns = ( 12.141 - 10.000 ) 
    Source Clock Delay      (SCD):    2.503ns
    Clock Pessimism Removal (CPR):    0.140ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.277ns (routing 0.777ns, distribution 1.500ns)
  Clock Net Delay (Destination): 1.959ns (routing 0.703ns, distribution 1.256ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[38])
                                                      0.569     3.072 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[38]
                         net (fo=20, routed)          5.519     8.591    d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[38]
    SLICE_X44Y103        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     8.690 r  d_1_i/ps8_0_axi_periph/m21_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[6]_INST_0/O
                         net (fo=64, routed)          1.408    10.098    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_wdata[6]
    SLICE_X39Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg15_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.959    12.141    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X39Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg15_reg[6]/C
                         clock pessimism              0.140    12.281    
                         clock uncertainty           -0.130    12.152    
    SLICE_X39Y148        FDRE (Setup_FFF2_SLICEM_C_D)
                                                      0.025    12.177    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg15_reg[6]
  -------------------------------------------------------------------
                         required time                         12.177    
                         arrival time                         -10.098    
  -------------------------------------------------------------------
                         slack                                  2.079    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMA/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.324%)  route 0.132ns (68.676%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      1.990ns (routing 0.703ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.296ns (routing 0.777ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.990     2.172    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X46Y7          FDCE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y7          FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.232 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q
                         net (fo=10, routed)          0.132     2.364    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/ADDRD1
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMA/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.522    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/WCLK
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMA/CLK
                         clock pessimism             -0.256     2.266    
    SLICE_X46Y6          RAMD32 (Hold_E5LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.354    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMA
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMA_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.324%)  route 0.132ns (68.676%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      1.990ns (routing 0.703ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.296ns (routing 0.777ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.990     2.172    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X46Y7          FDCE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y7          FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.232 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q
                         net (fo=10, routed)          0.132     2.364    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/ADDRD1
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMA_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.522    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/WCLK
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMA_D1/CLK
                         clock pessimism             -0.256     2.266    
    SLICE_X46Y6          RAMD32 (Hold_E6LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.354    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMB/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.324%)  route 0.132ns (68.676%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      1.990ns (routing 0.703ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.296ns (routing 0.777ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.990     2.172    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X46Y7          FDCE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y7          FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.232 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q
                         net (fo=10, routed)          0.132     2.364    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/ADDRD1
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMB/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.522    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/WCLK
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMB/CLK
                         clock pessimism             -0.256     2.266    
    SLICE_X46Y6          RAMD32 (Hold_F5LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.354    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMB
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMB_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.324%)  route 0.132ns (68.676%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      1.990ns (routing 0.703ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.296ns (routing 0.777ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.990     2.172    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X46Y7          FDCE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y7          FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.232 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q
                         net (fo=10, routed)          0.132     2.364    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/ADDRD1
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMB_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.522    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/WCLK
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMB_D1/CLK
                         clock pessimism             -0.256     2.266    
    SLICE_X46Y6          RAMD32 (Hold_F6LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.354    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMC/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.324%)  route 0.132ns (68.676%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      1.990ns (routing 0.703ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.296ns (routing 0.777ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.990     2.172    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X46Y7          FDCE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y7          FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.232 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q
                         net (fo=10, routed)          0.132     2.364    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/ADDRD1
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMC/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.522    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/WCLK
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMC/CLK
                         clock pessimism             -0.256     2.266    
    SLICE_X46Y6          RAMD32 (Hold_G5LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.354    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMC
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMC_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.324%)  route 0.132ns (68.676%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      1.990ns (routing 0.703ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.296ns (routing 0.777ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.990     2.172    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X46Y7          FDCE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y7          FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.232 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q
                         net (fo=10, routed)          0.132     2.364    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/ADDRD1
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMC_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.522    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/WCLK
    SLICE_X46Y6          RAMD32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMC_D1/CLK
                         clock pessimism             -0.256     2.266    
    SLICE_X46Y6          RAMD32 (Hold_G6LUT_SLICEM_CLK_WADR1)
                                                      0.088     2.354    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMC_D1
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMD/ADR1
                            (rising edge-triggered cell RAMS32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.324%)  route 0.132ns (68.676%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      1.990ns (routing 0.703ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.296ns (routing 0.777ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.990     2.172    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X46Y7          FDCE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y7          FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.232 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q
                         net (fo=10, routed)          0.132     2.364    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/ADDRD1
    SLICE_X46Y6          RAMS32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMD/ADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.522    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/WCLK
    SLICE_X46Y6          RAMS32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMD/CLK
                         clock pessimism             -0.256     2.266    
    SLICE_X46Y6          RAMS32 (Hold_H5LUT_SLICEM_CLK_ADR1)
                                                      0.088     2.354    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMD
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMD_D1/ADR1
                            (rising edge-triggered cell RAMS32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.324%)  route 0.132ns (68.676%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.172ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      1.990ns (routing 0.703ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.296ns (routing 0.777ns, distribution 1.519ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.990     2.172    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X46Y7          FDCE                                         r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y7          FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.060     2.232 r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/Q
                         net (fo=10, routed)          0.132     2.364    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/ADDRD1
    SLICE_X46Y6          RAMS32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMD_D1/ADR1
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.522    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/WCLK
    SLICE_X46Y6          RAMS32                                       r  d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMD_D1/CLK
                         clock pessimism             -0.256     2.266    
    SLICE_X46Y6          RAMS32 (Hold_H6LUT_SLICEM_CLK_ADR1)
                                                      0.088     2.354    d_1_i/ps8_0_axi_periph/m25_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_31_0_8/RAMD_D1
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_halt_reg_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.cnt_i_reg[2]/D
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.081ns (45.185%)  route 0.098ns (54.815%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.109ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.503ns
    Source Clock Delay      (SCD):    2.179ns
    Clock Pessimism Removal (CPR):    0.215ns
  Clock Net Delay (Source):      1.997ns (routing 0.703ns, distribution 1.294ns)
  Clock Net Delay (Destination): 2.277ns (routing 0.777ns, distribution 1.500ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.997     2.179    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/m_axi_s2mm_aclk
    SLICE_X62Y32         FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_halt_reg_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y32         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     2.237 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/sig_halt_reg_reg/Q
                         net (fo=75, routed)          0.073     2.311    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_data2addr_stop_req
    SLICE_X63Y32         LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.023     2.334 r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.cnt_i[2]_i_1__2/O
                         net (fo=1, routed)           0.025     2.359    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/addr_i_p1[2]
    SLICE_X63Y32         FDSE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.cnt_i_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.277     2.503    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/m_axi_s2mm_aclk
    SLICE_X63Y32         FDSE                                         r  d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.cnt_i_reg[2]/C
                         clock pessimism             -0.215     2.288    
    SLICE_X63Y32         FDSE (Hold_AFF_SLICEM_C_D)
                                                      0.060     2.348    d_1_i/axi_dma_tproc/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/INFERRED_GEN.cnt_i_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.348    
                         arrival time                           2.359    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_sreg/m_vector_i_reg[1073]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_reg_stall/skid_buffer_reg[1073]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.236ns  (logic 0.059ns (25.007%)  route 0.177ns (74.993%))
  Logic Levels:           0  
  Clock Path Skew:        0.164ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.516ns
    Source Clock Delay      (SCD):    2.142ns
    Clock Pessimism Removal (CPR):    0.210ns
  Clock Net Delay (Source):      1.960ns (routing 0.703ns, distribution 1.257ns)
  Clock Net Delay (Destination): 2.290ns (routing 0.777ns, distribution 1.513ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.960     2.142    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_sreg/aclk
    SLICE_X58Y2          FDRE                                         r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_sreg/m_vector_i_reg[1073]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y2          FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     2.201 r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_sreg/m_vector_i_reg[1073]/Q
                         net (fo=2, routed)           0.177     2.378    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_reg_stall/skid_buffer_reg[1144]_0[15]
    SLICE_X62Y1          FDRE                                         r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_reg_stall/skid_buffer_reg[1073]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.290     2.516    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_reg_stall/aclk
    SLICE_X62Y1          FDRE                                         r  d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_reg_stall/skid_buffer_reg[1073]/C
                         clock pessimism             -0.210     2.306    
    SLICE_X62Y1          FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     2.368    d_1_i/axi_smc/inst/s05_entry_pipeline/s05_mmu/inst/aw_reg_stall/skid_buffer_reg[1073]
  -------------------------------------------------------------------
                         required time                         -2.368    
                         arrival time                           2.378    
  -------------------------------------------------------------------
                         slack                                  0.010    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_pl_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location    Pin
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Min Period        n/a     HSADC/DCLK         n/a            4.000         10.000      6.000      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Min Period        n/a     HSDAC/DCLK         n/a            4.000         10.000      6.000      HSDAC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Min Period        n/a     HSDAC/DCLK         n/a            4.000         10.000      6.000      HSDAC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/DCLK
Min Period        n/a     PS8/MAXIGP0ACLK    n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
Min Period        n/a     PS8/SAXIGP0RCLK    n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0RCLK
Min Period        n/a     PS8/SAXIGP0WCLK    n/a            3.000         10.000      7.000      PS8_X0Y0    d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/SAXIGP0WCLK
Min Period        n/a     HSADC/PLL_MONCLK   n/a            2.500         10.000      7.500      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Low Pulse Width   Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Low Pulse Width   Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            3.000         5.000       2.000      MMCM_X0Y5   d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
High Pulse Width  Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y0  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y1  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y2  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
High Pulse Width  Slow    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
High Pulse Width  Fast    HSADC/DCLK         n/a            1.600         5.000       3.400      HSADC_X0Y3  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        0.134ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.015ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.958ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.134ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][1]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.398ns  (logic 2.552ns (58.031%)  route 1.846ns (41.969%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.386ns = ( 10.386 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.313ns (routing 1.464ns, distribution 0.849ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[1])
                                                      1.085     6.643 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[1]
                         net (fo=1, routed)           0.026     6.669    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_66
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     6.879 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[1]
                         net (fo=1, routed)           0.026     6.905    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_66
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     7.115 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[1]
                         net (fo=1, routed)           0.026     7.141    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_66
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     7.351 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[1]
                         net (fo=1, routed)           0.026     7.377    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_66
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     7.587 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[1]
                         net (fo=1, routed)           0.026     7.613    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_66
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     7.823 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[1]
                         net (fo=1, routed)           0.026     7.849    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_66
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     8.059 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[1]
                         net (fo=1, routed)           0.026     8.085    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_66
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_DOUTBDOUT[1])
                                                      0.117     8.202 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[1]
                         net (fo=3, routed)           0.912     9.114    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[1]
    SLICE_X43Y223        LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     9.204 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[1]_i_1/O
                         net (fo=21, routed)          0.751     9.956    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[1]
    SLICE_X31Y210        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.313    10.386    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X31Y210        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][1]/C
                         clock pessimism             -0.259    10.127    
                         clock uncertainty           -0.062    10.065    
    SLICE_X31Y210        FDCE (Setup_EFF_SLICEM_C_D)
                                                      0.025    10.090    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[7][1]
  -------------------------------------------------------------------
                         required time                         10.090    
                         arrival time                          -9.956    
  -------------------------------------------------------------------
                         slack                                  0.134    

Slack (MET) :             0.135ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[6][2]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.396ns  (logic 2.542ns (57.831%)  route 1.854ns (42.169%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.385ns = ( 10.385 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.312ns (routing 1.464ns, distribution 0.848ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[2])
                                                      1.075     6.633 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[2]
                         net (fo=1, routed)           0.022     6.655    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_65
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     6.865 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[2]
                         net (fo=1, routed)           0.022     6.887    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_65
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     7.097 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[2]
                         net (fo=1, routed)           0.022     7.119    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_65
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     7.329 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[2]
                         net (fo=1, routed)           0.022     7.351    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_65
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     7.561 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[2]
                         net (fo=1, routed)           0.022     7.583    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_65
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     7.793 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[2]
                         net (fo=1, routed)           0.022     7.815    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_65
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     8.025 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[2]
                         net (fo=1, routed)           0.022     8.047    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_65
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_DOUTBDOUT[2])
                                                      0.117     8.164 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[2]
                         net (fo=3, routed)           0.872     9.036    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[2]
    SLICE_X44Y205        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     9.126 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[2]_i_1/O
                         net (fo=21, routed)          0.827     9.954    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[2]
    SLICE_X27Y206        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[6][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.312    10.385    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X27Y206        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[6][2]/C
                         clock pessimism             -0.259    10.126    
                         clock uncertainty           -0.062    10.064    
    SLICE_X27Y206        FDCE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    10.089    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[6][2]
  -------------------------------------------------------------------
                         required time                         10.089    
                         arrival time                          -9.954    
  -------------------------------------------------------------------
                         slack                                  0.135    

Slack (MET) :             0.141ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[12][7]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.393ns  (logic 2.476ns (56.365%)  route 1.917ns (43.635%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.388ns = ( 10.388 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.315ns (routing 1.464ns, distribution 0.851ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[7])
                                                      1.062     6.620 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[7]
                         net (fo=1, routed)           0.028     6.648    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_60
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     6.858 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[7]
                         net (fo=1, routed)           0.028     6.886    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_60
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.096 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.124    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_60
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.334 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.362    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_60
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.572 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.600    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_60
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.810 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.838    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_60
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     8.048 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[7]
                         net (fo=1, routed)           0.028     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_60
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_DOUTBDOUT[7])
                                                      0.117     8.193 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[7]
                         net (fo=3, routed)           0.883     9.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[7]
    SLICE_X46Y222        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.037     9.113 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[7]_i_2/O
                         net (fo=21, routed)          0.838     9.951    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[7]
    SLICE_X33Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[12][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.315    10.388    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X33Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[12][7]/C
                         clock pessimism             -0.259    10.129    
                         clock uncertainty           -0.062    10.067    
    SLICE_X33Y208        FDCE (Setup_HFF_SLICEL_C_D)
                                                      0.025    10.092    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[12][7]
  -------------------------------------------------------------------
                         required time                         10.092    
                         arrival time                          -9.951    
  -------------------------------------------------------------------
                         slack                                  0.141    

Slack (MET) :             0.147ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[3][7]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.395ns  (logic 2.476ns (56.332%)  route 1.919ns (43.668%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.420ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.397ns = ( 10.397 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.324ns (routing 1.464ns, distribution 0.860ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[7])
                                                      1.062     6.620 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[7]
                         net (fo=1, routed)           0.028     6.648    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_60
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     6.858 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[7]
                         net (fo=1, routed)           0.028     6.886    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_60
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.096 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.124    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_60
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.334 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.362    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_60
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.572 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.600    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_60
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.810 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.838    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_60
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     8.048 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[7]
                         net (fo=1, routed)           0.028     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_60
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_DOUTBDOUT[7])
                                                      0.117     8.193 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[7]
                         net (fo=3, routed)           0.883     9.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[7]
    SLICE_X46Y222        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.037     9.113 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[7]_i_2/O
                         net (fo=21, routed)          0.841     9.953    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[7]
    SLICE_X34Y216        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[3][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.324    10.397    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X34Y216        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[3][7]/C
                         clock pessimism             -0.259    10.138    
                         clock uncertainty           -0.062    10.075    
    SLICE_X34Y216        FDCE (Setup_EFF_SLICEM_C_D)
                                                      0.025    10.100    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[3][7]
  -------------------------------------------------------------------
                         required time                         10.100    
                         arrival time                          -9.953    
  -------------------------------------------------------------------
                         slack                                  0.147    

Slack (MET) :             0.147ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[14][17]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.391ns  (logic 2.467ns (56.188%)  route 1.924ns (43.812%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.425ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.392ns = ( 10.392 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.319ns (routing 1.464ns, distribution 0.855ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTPB[1])
                                                      1.055     6.613 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTPB[1]
                         net (fo=1, routed)           0.031     6.644    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_138
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[1]_CASDOUTPB[1])
                                                      0.210     6.854 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTPB[1]
                         net (fo=1, routed)           0.031     6.885    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_138
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[1]_CASDOUTPB[1])
                                                      0.210     7.095 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTPB[1]
                         net (fo=1, routed)           0.031     7.126    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_138
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[1]_CASDOUTPB[1])
                                                      0.210     7.336 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTPB[1]
                         net (fo=1, routed)           0.031     7.367    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_138
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[1]_CASDOUTPB[1])
                                                      0.210     7.577 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTPB[1]
                         net (fo=1, routed)           0.031     7.608    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_138
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[1]_CASDOUTPB[1])
                                                      0.210     7.818 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTPB[1]
                         net (fo=1, routed)           0.031     7.849    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_138
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[1]_CASDOUTPB[1])
                                                      0.210     8.059 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTPB[1]
                         net (fo=1, routed)           0.031     8.090    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_138
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINPB[1]_DOUTPBDOUTP[1])
                                                      0.117     8.207 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTPBDOUTP[1]
                         net (fo=3, routed)           0.905     9.112    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[17]
    SLICE_X43Y224        LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.035     9.147 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt[0][17]_i_1/O
                         net (fo=19, routed)          0.801     9.949    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt[0][17]_i_1_n_0
    SLICE_X32Y213        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[14][17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.319    10.392    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X32Y213        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[14][17]/C
                         clock pessimism             -0.259    10.133    
                         clock uncertainty           -0.062    10.071    
    SLICE_X32Y213        FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    10.096    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[14][17]
  -------------------------------------------------------------------
                         required time                         10.096    
                         arrival time                          -9.949    
  -------------------------------------------------------------------
                         slack                                  0.147    

Slack (MET) :             0.149ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[11][12]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.368ns  (logic 2.452ns (56.142%)  route 1.916ns (43.858%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.446ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.371ns = ( 10.371 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.298ns (routing 1.464ns, distribution 0.834ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[12])
                                                      1.039     6.597 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[12]
                         net (fo=1, routed)           0.028     6.625    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_55
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[12]_CASDOUTB[12])
                                                      0.210     6.835 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[12]
                         net (fo=1, routed)           0.028     6.863    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_55
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[12]_CASDOUTB[12])
                                                      0.210     7.073 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[12]
                         net (fo=1, routed)           0.028     7.101    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_55
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[12]_CASDOUTB[12])
                                                      0.210     7.311 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[12]
                         net (fo=1, routed)           0.028     7.339    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_55
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[12]_CASDOUTB[12])
                                                      0.210     7.549 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[12]
                         net (fo=1, routed)           0.028     7.577    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_55
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[12]_CASDOUTB[12])
                                                      0.210     7.787 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[12]
                         net (fo=1, routed)           0.028     7.815    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_55
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[12]_CASDOUTB[12])
                                                      0.210     8.025 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[12]
                         net (fo=1, routed)           0.028     8.053    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_55
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[12]_DOUTBDOUT[12])
                                                      0.117     8.170 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[12]
                         net (fo=3, routed)           0.874     9.044    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[12]
    SLICE_X43Y222        LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     9.080 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt[0][12]_i_1/O
                         net (fo=20, routed)          0.846     9.926    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt[0][12]_i_1_n_0
    SLICE_X26Y210        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[11][12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.298    10.371    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X26Y210        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[11][12]/C
                         clock pessimism             -0.259    10.112    
                         clock uncertainty           -0.062    10.050    
    SLICE_X26Y210        FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    10.075    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[11][12]
  -------------------------------------------------------------------
                         required time                         10.075    
                         arrival time                          -9.926    
  -------------------------------------------------------------------
                         slack                                  0.149    

Slack (MET) :             0.156ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[10][8]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.380ns  (logic 2.451ns (55.964%)  route 1.929ns (44.036%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.427ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.390ns = ( 10.390 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.317ns (routing 1.464ns, distribution 0.853ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[8])
                                                      1.039     6.597 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[8]
                         net (fo=1, routed)           0.027     6.624    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_59
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[8]_CASDOUTB[8])
                                                      0.210     6.834 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[8]
                         net (fo=1, routed)           0.027     6.861    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_59
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[8]_CASDOUTB[8])
                                                      0.210     7.071 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[8]
                         net (fo=1, routed)           0.027     7.098    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_59
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[8]_CASDOUTB[8])
                                                      0.210     7.308 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[8]
                         net (fo=1, routed)           0.027     7.335    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_59
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[8]_CASDOUTB[8])
                                                      0.210     7.545 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[8]
                         net (fo=1, routed)           0.027     7.572    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_59
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[8]_CASDOUTB[8])
                                                      0.210     7.782 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[8]
                         net (fo=1, routed)           0.027     7.809    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_59
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[8]_CASDOUTB[8])
                                                      0.210     8.019 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[8]
                         net (fo=1, routed)           0.027     8.046    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_59
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[8]_DOUTBDOUT[8])
                                                      0.117     8.163 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[8]
                         net (fo=3, routed)           0.897     9.060    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[8]
    SLICE_X47Y220        LUT6 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.035     9.095 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt[0][8]_i_1/O
                         net (fo=20, routed)          0.843     9.938    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt[0][8]_i_1_n_0
    SLICE_X36Y209        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[10][8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.317    10.390    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X36Y209        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[10][8]/C
                         clock pessimism             -0.259    10.131    
                         clock uncertainty           -0.062    10.069    
    SLICE_X36Y209        FDCE (Setup_AFF_SLICEL_C_D)
                                                      0.025    10.094    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[10][8]
  -------------------------------------------------------------------
                         required time                         10.094    
                         arrival time                          -9.938    
  -------------------------------------------------------------------
                         slack                                  0.156    

Slack (MET) :             0.157ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[5][1]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.377ns  (logic 2.552ns (58.310%)  route 1.825ns (41.690%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.429ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.388ns = ( 10.388 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.315ns (routing 1.464ns, distribution 0.851ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[1])
                                                      1.085     6.643 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[1]
                         net (fo=1, routed)           0.026     6.669    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_66
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     6.879 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[1]
                         net (fo=1, routed)           0.026     6.905    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_66
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     7.115 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[1]
                         net (fo=1, routed)           0.026     7.141    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_66
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     7.351 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[1]
                         net (fo=1, routed)           0.026     7.377    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_66
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     7.587 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[1]
                         net (fo=1, routed)           0.026     7.613    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_66
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     7.823 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[1]
                         net (fo=1, routed)           0.026     7.849    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_66
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_CASDOUTB[1])
                                                      0.210     8.059 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[1]
                         net (fo=1, routed)           0.026     8.085    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_66
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[1]_DOUTBDOUT[1])
                                                      0.117     8.202 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[1]
                         net (fo=3, routed)           0.912     9.114    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[1]
    SLICE_X43Y223        LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     9.204 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[1]_i_1/O
                         net (fo=21, routed)          0.730     9.935    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[1]
    SLICE_X32Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[5][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.315    10.388    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X32Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[5][1]/C
                         clock pessimism             -0.259    10.129    
                         clock uncertainty           -0.062    10.067    
    SLICE_X32Y208        FDCE (Setup_AFF2_SLICEL_C_D)
                                                      0.025    10.092    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[5][1]
  -------------------------------------------------------------------
                         required time                         10.092    
                         arrival time                          -9.935    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][7]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.378ns  (logic 2.476ns (56.560%)  route 1.902ns (43.440%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.428ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.389ns = ( 10.389 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.316ns (routing 1.464ns, distribution 0.852ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[7])
                                                      1.062     6.620 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[7]
                         net (fo=1, routed)           0.028     6.648    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_60
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     6.858 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[7]
                         net (fo=1, routed)           0.028     6.886    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_60
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.096 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.124    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_60
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.334 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.362    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_60
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.572 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.600    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_60
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     7.810 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[7]
                         net (fo=1, routed)           0.028     7.838    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_60
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_CASDOUTB[7])
                                                      0.210     8.048 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[7]
                         net (fo=1, routed)           0.028     8.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_60
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[7]_DOUTBDOUT[7])
                                                      0.117     8.193 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[7]
                         net (fo=3, routed)           0.883     9.076    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[7]
    SLICE_X46Y222        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.037     9.113 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[7]_i_2/O
                         net (fo=21, routed)          0.823     9.936    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[7]
    SLICE_X33Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.316    10.389    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X33Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][7]/C
                         clock pessimism             -0.259    10.130    
                         clock uncertainty           -0.062    10.068    
    SLICE_X33Y207        FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    10.093    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[2][7]
  -------------------------------------------------------------------
                         required time                         10.093    
                         arrival time                          -9.936    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.158ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
                            (rising edge-triggered cell RAMB36E2 clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[3][2]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.371ns  (logic 2.542ns (58.160%)  route 1.829ns (41.840%))
  Logic Levels:           8  (LUT6=1 RAMB36E2=7)
  Clock Path Skew:        -0.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.383ns = ( 10.383 - 5.000 ) 
    Source Clock Delay      (SCD):    5.558ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.943ns (routing 1.611ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.310ns (routing 1.464ns, distribution 0.846ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.943     5.558    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/c_clk_i
    RAMB36_X7Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X7Y42         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKBWRCLK_CASDOUTB[2])
                                                      1.075     6.633 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CASDOUTB[2]
                         net (fo=1, routed)           0.022     6.655    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0_n_65
    RAMB36_X7Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     6.865 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CASDOUTB[2]
                         net (fo=1, routed)           0.022     6.887    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1_n_65
    RAMB36_X7Y44         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     7.097 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CASDOUTB[2]
                         net (fo=1, routed)           0.022     7.119    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2_n_65
    RAMB36_X7Y45         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     7.329 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CASDOUTB[2]
                         net (fo=1, routed)           0.022     7.351    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3_n_65
    RAMB36_X7Y46         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     7.561 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CASDOUTB[2]
                         net (fo=1, routed)           0.022     7.583    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4_n_65
    RAMB36_X7Y47         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     7.793 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5/CASDOUTB[2]
                         net (fo=1, routed)           0.022     7.815    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_5_n_65
    RAMB36_X7Y48         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_CASDOUTB[2])
                                                      0.210     8.025 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6/CASDOUTB[2]
                         net (fo=1, routed)           0.022     8.047    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_6_n_65
    RAMB36_X7Y49         RAMB36E2 (Prop_RAMB36E2_RAMB36_CASDINB[2]_DOUTBDOUT[2])
                                                      0.117     8.164 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/DOUTBDOUT[2]
                         net (fo=3, routed)           0.872     9.036    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dmem_r_dt[2]
    SLICE_X44Y205        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     9.126 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_cfg_dt[2]_i_1/O
                         net (fo=21, routed)          0.802     9.929    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/p_1_in[2]
    SLICE_X27Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[3][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.310    10.383    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X27Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[3][2]/C
                         clock pessimism             -0.259    10.124    
                         clock uncertainty           -0.062    10.062    
    SLICE_X27Y207        FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025    10.087    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[3][2]
  -------------------------------------------------------------------
                         required time                         10.087    
                         arrival time                          -9.929    
  -------------------------------------------------------------------
                         slack                                  0.158    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_remainder_o_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[6]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.182ns  (logic 0.058ns (31.868%)  route 0.124ns (68.132%))
  Logic Levels:           0  
  Clock Path Skew:        0.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.307ns
    Source Clock Delay      (SCD):    5.458ns
    Clock Pessimism Removal (CPR):    -0.256ns
  Clock Net Delay (Source):      2.385ns (routing 1.464ns, distribution 0.921ns)
  Clock Net Delay (Destination): 2.692ns (routing 1.611ns, distribution 1.081ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.385     5.458    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/c_clk_i
    SLICE_X15Y217        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_remainder_o_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y217        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     5.516 r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_remainder_o_reg[6]/Q
                         net (fo=1, routed)           0.124     5.640    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_s[6]
    SLICE_X17Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.692     5.307    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X17Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[6]/C
                         clock pessimism              0.256     5.563    
    SLICE_X17Y212        FDCE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     5.625    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[6]
  -------------------------------------------------------------------
                         required time                         -5.625    
                         arrival time                           5.640    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.019ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.202ns  (logic 0.114ns (56.569%)  route 0.088ns (43.431%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.122ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.376ns
    Source Clock Delay      (SCD):    5.508ns
    Clock Pessimism Removal (CPR):    -0.254ns
  Clock Net Delay (Source):      2.435ns (routing 1.464ns, distribution 0.971ns)
  Clock Net Delay (Destination): 2.761ns (routing 1.611ns, distribution 1.150ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.435     5.508    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y210        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y210        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     5.566 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/Q
                         net (fo=9, routed)           0.064     5.630    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[7]
    SLICE_X59Y209        LUT2 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.056     5.686 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[7]_i_1__15/O
                         net (fo=1, routed)           0.024     5.710    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[7]_i_1__15_n_0
    SLICE_X59Y209        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.761     5.376    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y209        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                         clock pessimism              0.254     5.630    
    SLICE_X59Y209        FDCE (Hold_FFF_SLICEL_C_D)
                                                      0.060     5.690    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]
  -------------------------------------------------------------------
                         required time                         -5.690    
                         arrival time                           5.710    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.023ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[cfg_port_time]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x2_ctrl_reg[cfg_port_time]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.198ns  (logic 0.060ns (30.303%)  route 0.138ns (69.697%))
  Logic Levels:           0  
  Clock Path Skew:        0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.363ns
    Source Clock Delay      (SCD):    5.502ns
    Clock Pessimism Removal (CPR):    -0.254ns
  Clock Net Delay (Source):      2.429ns (routing 1.464ns, distribution 0.965ns)
  Clock Net Delay (Destination): 2.748ns (routing 1.611ns, distribution 1.137ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.429     5.502    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X40Y222        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[cfg_port_time]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y222        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.060     5.562 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[cfg_port_time]/Q
                         net (fo=1, routed)           0.138     5.700    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[cfg_port_time]__0
    SLICE_X43Y222        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x2_ctrl_reg[cfg_port_time]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.748     5.363    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X43Y222        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x2_ctrl_reg[cfg_port_time]/C
                         clock pessimism              0.254     5.617    
    SLICE_X43Y222        FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     5.677    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x2_ctrl_reg[cfg_port_time]
  -------------------------------------------------------------------
                         required time                         -5.677    
                         arrival time                           5.700    
  -------------------------------------------------------------------
                         slack                                  0.023    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.174ns  (logic 0.081ns (46.461%)  route 0.093ns (53.539%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.403ns
    Source Clock Delay      (SCD):    5.568ns
    Clock Pessimism Removal (CPR):    -0.250ns
  Clock Net Delay (Source):      2.495ns (routing 1.464ns, distribution 1.031ns)
  Clock Net Delay (Destination): 2.788ns (routing 1.611ns, distribution 1.177ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.495     5.568    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y275        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y275        FDPE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     5.627 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/Q
                         net (fo=8, routed)           0.067     5.695    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/wr_gptr_p1[0]
    SLICE_X60Y275        LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.022     5.717 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r[3]_i_1__23/O
                         net (fo=1, routed)           0.026     5.743    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/p_0_in[3]
    SLICE_X60Y275        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.788     5.403    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X60Y275        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/C
                         clock pessimism              0.250     5.653    
    SLICE_X60Y275        FDCE (Hold_EFF_SLICEM_C_D)
                                                      0.060     5.713    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -5.713    
                         arrival time                           5.743    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_id_imm_dt_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.059ns (41.259%)  route 0.084ns (58.741%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.348ns
    Source Clock Delay      (SCD):    5.497ns
    Clock Pessimism Removal (CPR):    -0.203ns
  Clock Net Delay (Source):      2.424ns (routing 1.464ns, distribution 0.960ns)
  Clock Net Delay (Destination): 2.733ns (routing 1.611ns, distribution 1.122ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.424     5.497    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X40Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_id_imm_dt_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y216        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     5.556 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_id_imm_dt_reg[3]/Q
                         net (fo=1, routed)           0.084     5.640    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_id_imm_dt[3]
    SLICE_X40Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.733     5.348    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X40Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[3]/C
                         clock pessimism              0.203     5.551    
    SLICE_X40Y218        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.060     5.611    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/r_rd_imm_dt_reg[3]
  -------------------------------------------------------------------
                         required time                         -5.611    
                         arrival time                           5.640    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.206ns  (logic 0.092ns (44.597%)  route 0.114ns (55.403%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.113ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.433ns
    Source Clock Delay      (SCD):    5.562ns
    Clock Pessimism Removal (CPR):    -0.242ns
  Clock Net Delay (Source):      2.489ns (routing 1.464ns, distribution 1.025ns)
  Clock Net Delay (Destination): 2.818ns (routing 1.611ns, distribution 1.207ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.489     5.562    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X62Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y217        FDCE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     5.622 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_r_reg/Q
                         net (fo=20, routed)          0.105     5.727    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/clear_r
    SLICE_X64Y215        LUT2 (Prop_H5LUT_SLICEL_I1_O)
                                                      0.032     5.759 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[0]_i_1__21/O
                         net (fo=1, routed)           0.009     5.768    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r[0]_i_1__21_n_0
    SLICE_X64Y215        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.818     5.433    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X64Y215        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                         clock pessimism              0.242     5.675    
    SLICE_X64Y215        FDCE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     5.737    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[11].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]
  -------------------------------------------------------------------
                         required time                         -5.737    
                         arrival time                           5.768    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.988%)  route 0.044ns (53.012%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.034ns
    Source Clock Delay      (SCD):    3.185ns
    Clock Pessimism Removal (CPR):    -0.157ns
  Clock Net Delay (Source):      1.445ns (routing 0.877ns, distribution 0.568ns)
  Clock Net Delay (Destination): 1.627ns (routing 0.978ns, distribution 0.649ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.445     3.185    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X25Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X25Y240        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     3.224 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[8]/Q
                         net (fo=3, routed)           0.044     3.268    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r[8]
    SLICE_X25Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.627     3.034    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X25Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[8]/C
                         clock pessimism              0.157     3.191    
    SLICE_X25Y240        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     3.237    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.237    
                         arrival time                           3.268    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[3][5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_curr_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.101ns  (logic 0.052ns (51.647%)  route 0.049ns (48.353%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.022ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.021ns
    Source Clock Delay      (SCD):    3.172ns
    Clock Pessimism Removal (CPR):    -0.173ns
  Clock Net Delay (Source):      1.432ns (routing 0.877ns, distribution 0.555ns)
  Clock Net Delay (Destination): 1.614ns (routing 0.978ns, distribution 0.636ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.432     3.172    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X35Y215        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[3][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y215        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.210 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[3][5]/Q
                         net (fo=5, routed)           0.031     3.240    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/pc_stack_inst/PC_curr_reg[11]_3[5]
    SLICE_X35Y216        LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.014     3.254 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/pc_stack_inst/PC_curr[5]_i_1/O
                         net (fo=1, routed)           0.018     3.272    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/pc_stack_inst_n_16
    SLICE_X35Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_curr_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.614     3.021    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X35Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_curr_reg[5]/C
                         clock pessimism              0.173     3.194    
    SLICE_X35Y216        FDRE (Hold_AFF_SLICEM_C_D)
                                                      0.046     3.240    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/PC_curr_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.240    
                         arrival time                           3.272    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[56]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][56]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.059ns (31.551%)  route 0.128ns (68.449%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.376ns
    Source Clock Delay      (SCD):    5.537ns
    Clock Pessimism Removal (CPR):    -0.254ns
  Clock Net Delay (Source):      2.464ns (routing 1.464ns, distribution 1.000ns)
  Clock Net Delay (Destination): 2.761ns (routing 1.611ns, distribution 1.150ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.464     5.537    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[56]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y194        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.059     5.596 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[56]/Q
                         net (fo=1, routed)           0.128     5.724    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[56]
    SLICE_X58Y196        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][56]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.761     5.376    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X58Y196        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][56]/C
                         clock pessimism              0.254     5.630    
    SLICE_X58Y196        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.060     5.690    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.gen_stage.doutb_pipe_reg[0][56]
  -------------------------------------------------------------------
                         required time                         -5.690    
                         arrival time                           5.724    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_remainder_o_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[19]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.059ns (45.385%)  route 0.071ns (54.615%))
  Logic Levels:           0  
  Clock Path Skew:        0.035ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    5.299ns
    Source Clock Delay      (SCD):    5.470ns
    Clock Pessimism Removal (CPR):    -0.205ns
  Clock Net Delay (Source):      2.397ns (routing 1.464ns, distribution 0.933ns)
  Clock Net Delay (Destination): 2.684ns (routing 1.611ns, distribution 1.073ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.397     5.470    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/c_clk_i
    SLICE_X15Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_remainder_o_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y221        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     5.529 r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.DIV/div_remainder_o_reg[19]/Q
                         net (fo=1, routed)           0.071     5.600    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_s[19]
    SLICE_X15Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.684     5.299    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X15Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[19]/C
                         clock pessimism              0.205     5.504    
    SLICE_X15Y220        FDCE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     5.566    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[19]
  -------------------------------------------------------------------
                         required time                         -5.566    
                         arrival time                           5.600    
  -------------------------------------------------------------------
                         slack                                  0.033    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_core_0
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y42  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y43  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y52  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y53  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X5Y46  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_12/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X5Y47  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_13/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB18_X5Y82  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_14/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y44  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y45  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y46  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_4/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y59  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y59  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y50  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y50  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y54  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y54  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y52  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y52  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y49  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y49  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y59  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y59  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y50  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y50  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y54  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y54  d_1_i/qick_processor_0/WAVE_FIFO[0].wave_fifo_inst/fifo_mem/RAM_reg_2/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y52  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y52  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_0/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y49  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X6Y49  d_1_i/qick_processor_0/WAVE_FIFO[1].wave_fifo_inst/fifo_mem/RAM_reg_1/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       14.014ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.026ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       24.468ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             14.014ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        3.239ns  (logic 0.261ns (8.058%)  route 2.978ns (91.942%))
  Logic Levels:           2  (LUT3=1 LUT6=1)
  Clock Path Skew:        -7.511ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns = ( 25.000 - 25.000 ) 
    Source Clock Delay      (SCD):    7.511ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.846ns (routing 0.533ns, distribution 1.313ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.846     7.511    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X101Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y332       FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     7.592 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDO_reg/Q
                         net (fo=1, routed)           1.905     9.497    dbg_hub/inst/BSCANID.u_xsdbm_id/TDO
    SLICE_X100Y92        LUT3 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.090     9.587 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch_i_1/O
                         net (fo=2, routed)           0.140     9.727    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_tdo[0]
    SLICE_X99Y91         LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     9.817 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdo_INST_0/O
                         net (fo=1, routed)           0.933    10.750    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TDO
    CONFIG_SITE_X0Y0     BSCANE2                                      r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                         clock pessimism              0.000    25.000    
                         clock uncertainty           -0.235    24.765    
    CONFIG_SITE_X0Y0     BSCANE2 (Setup_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TDO)
                                                      0.000    24.765    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst
  -------------------------------------------------------------------
                         required time                         24.765    
                         arrival time                         -10.750    
  -------------------------------------------------------------------
                         slack                                 14.014    

Slack (MET) :             19.142ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.596ns  (logic 5.276ns (61.377%)  route 3.320ns (38.623%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.048ns = ( 53.048 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.647ns (routing 0.483ns, distribution 1.164ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.152    33.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y331       LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050    33.070 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.085    33.155    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X101Y332       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089    33.244 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.352    33.596    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.647    53.048    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/C
                         clock pessimism              0.000    53.048    
                         clock uncertainty           -0.235    52.812    
    SLICE_X100Y348       FDRE (Setup_FFF2_SLICEL_C_R)
                                                     -0.074    52.738    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]
  -------------------------------------------------------------------
                         required time                         52.738    
                         arrival time                         -33.596    
  -------------------------------------------------------------------
                         slack                                 19.142    

Slack (MET) :             19.142ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.596ns  (logic 5.276ns (61.377%)  route 3.320ns (38.623%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.048ns = ( 53.048 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.647ns (routing 0.483ns, distribution 1.164ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.152    33.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y331       LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050    33.070 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.085    33.155    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X101Y332       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089    33.244 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.352    33.596    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.647    53.048    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/C
                         clock pessimism              0.000    53.048    
                         clock uncertainty           -0.235    52.812    
    SLICE_X100Y348       FDRE (Setup_HFF_SLICEL_C_R)
                                                     -0.074    52.738    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]
  -------------------------------------------------------------------
                         required time                         52.738    
                         arrival time                         -33.596    
  -------------------------------------------------------------------
                         slack                                 19.142    

Slack (MET) :             19.142ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.596ns  (logic 5.276ns (61.377%)  route 3.320ns (38.623%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.048ns = ( 53.048 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.647ns (routing 0.483ns, distribution 1.164ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.152    33.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y331       LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050    33.070 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.085    33.155    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X101Y332       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089    33.244 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.352    33.596    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.647    53.048    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/C
                         clock pessimism              0.000    53.048    
                         clock uncertainty           -0.235    52.812    
    SLICE_X100Y348       FDRE (Setup_HFF2_SLICEL_C_R)
                                                     -0.074    52.738    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]
  -------------------------------------------------------------------
                         required time                         52.738    
                         arrival time                         -33.596    
  -------------------------------------------------------------------
                         slack                                 19.142    

Slack (MET) :             19.142ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.596ns  (logic 5.276ns (61.377%)  route 3.320ns (38.623%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.048ns = ( 53.048 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.647ns (routing 0.483ns, distribution 1.164ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.152    33.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y331       LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050    33.070 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.085    33.155    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X101Y332       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089    33.244 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.352    33.596    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.647    53.048    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]/C
                         clock pessimism              0.000    53.048    
                         clock uncertainty           -0.235    52.812    
    SLICE_X100Y348       FDRE (Setup_GFF_SLICEL_C_R)
                                                     -0.074    52.738    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[3]
  -------------------------------------------------------------------
                         required time                         52.738    
                         arrival time                         -33.596    
  -------------------------------------------------------------------
                         slack                                 19.142    

Slack (MET) :             19.142ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.596ns  (logic 5.276ns (61.377%)  route 3.320ns (38.623%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.048ns = ( 53.048 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.647ns (routing 0.483ns, distribution 1.164ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.152    33.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y331       LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050    33.070 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.085    33.155    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X101Y332       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089    33.244 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.352    33.596    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.647    53.048    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]/C
                         clock pessimism              0.000    53.048    
                         clock uncertainty           -0.235    52.812    
    SLICE_X100Y348       FDRE (Setup_GFF2_SLICEL_C_R)
                                                     -0.074    52.738    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[4]
  -------------------------------------------------------------------
                         required time                         52.738    
                         arrival time                         -33.596    
  -------------------------------------------------------------------
                         slack                                 19.142    

Slack (MET) :             19.142ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.596ns  (logic 5.276ns (61.377%)  route 3.320ns (38.623%))
  Logic Levels:           3  (LUT4=1 LUT5=2)
  Clock Path Skew:        3.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.048ns = ( 53.048 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.647ns (routing 0.483ns, distribution 1.164ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           2.152    33.020    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y331       LUT4 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050    33.070 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
                         net (fo=1, routed)           0.085    33.155    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
    SLICE_X101Y332       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089    33.244 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
                         net (fo=6, routed)           0.352    33.596    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.647    53.048    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X100Y348       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]/C
                         clock pessimism              0.000    53.048    
                         clock uncertainty           -0.235    52.812    
    SLICE_X100Y348       FDRE (Setup_EFF_SLICEL_C_R)
                                                     -0.074    52.738    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[5]
  -------------------------------------------------------------------
                         required time                         52.738    
                         arrival time                         -33.596    
  -------------------------------------------------------------------
                         slack                                 19.142    

Slack (MET) :             19.392ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.346ns  (logic 5.172ns (61.973%)  route 3.174ns (38.027%))
  Logic Levels:           2  (LUT2=1 LUT5=1)
  Clock Path Skew:        3.032ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.973    32.840    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y319       LUT2 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035    32.875 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.470    33.346    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_CE
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              0.000    53.032    
                         clock uncertainty           -0.235    52.796    
    SLICE_X101Y332       FDCE (Setup_AFF2_SLICEL_C_CE)
                                                     -0.059    52.737    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                         52.737    
                         arrival time                         -33.346    
  -------------------------------------------------------------------
                         slack                                 19.392    

Slack (MET) :             19.392ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.346ns  (logic 5.172ns (61.973%)  route 3.174ns (38.027%))
  Logic Levels:           2  (LUT2=1 LUT5=1)
  Clock Path Skew:        3.032ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.973    32.840    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y319       LUT2 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035    32.875 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.470    33.346    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_CE
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
                         clock pessimism              0.000    53.032    
                         clock uncertainty           -0.235    52.796    
    SLICE_X101Y332       FDCE (Setup_BFF2_SLICEL_C_CE)
                                                     -0.059    52.737    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]
  -------------------------------------------------------------------
                         required time                         52.737    
                         arrival time                         -33.346    
  -------------------------------------------------------------------
                         slack                                 19.392    

Slack (MET) :             19.392ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        8.346ns  (logic 5.172ns (61.973%)  route 3.174ns (38.027%))
  Logic Levels:           2  (LUT2=1 LUT5=1)
  Clock Path Skew:        3.032ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_SHIFT)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/SHIFT
                         net (fo=37, routed)          0.731    30.831    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_shift
    SLICE_X99Y91         LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037    30.868 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
                         net (fo=4, routed)           1.973    32.840    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
    SLICE_X101Y319       LUT2 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035    32.875 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_1/O
                         net (fo=10, routed)          0.470    33.346    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_CE
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              0.000    53.032    
                         clock uncertainty           -0.235    52.796    
    SLICE_X101Y332       FDCE (Setup_CFF2_SLICEL_C_CE)
                                                     -0.059    52.737    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         52.737    
                         arrival time                         -33.346    
  -------------------------------------------------------------------
                         slack                                 19.392    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[20]/D
                            (rising edge-triggered cell FDSE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.185ns  (logic 0.093ns (50.270%)  route 0.092ns (49.730%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.099ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.512ns
    Source Clock Delay      (SCD):    3.019ns
    Clock Pessimism Removal (CPR):    4.394ns
  Clock Net Delay (Source):      1.618ns (routing 0.483ns, distribution 1.135ns)
  Clock Net Delay (Destination): 1.847ns (routing 0.533ns, distribution 1.314ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.618     3.019    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X98Y85         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y85         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     3.077 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[21]/Q
                         net (fo=1, routed)           0.066     3.143    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid__0[21]
    SLICE_X99Y85         LUT2 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.035     3.178 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[20]_i_1/O
                         net (fo=1, routed)           0.026     3.204    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[20]_i_1_n_0
    SLICE_X99Y85         FDSE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.847     7.512    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X99Y85         FDSE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[20]/C
                         clock pessimism             -4.394     3.118    
    SLICE_X99Y85         FDSE (Hold_EFF_SLICEM_C_D)
                                                      0.060     3.178    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[20]
  -------------------------------------------------------------------
                         required time                         -3.178    
                         arrival time                           3.204    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.081ns  (logic 0.038ns (46.904%)  route 0.043ns (53.096%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.386ns
    Source Clock Delay      (SCD):    2.190ns
    Clock Pessimism Removal (CPR):    4.191ns
  Clock Net Delay (Source):      0.997ns (routing 0.294ns, distribution 0.703ns)
  Clock Net Delay (Destination): 1.126ns (routing 0.330ns, distribution 0.796ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.997     2.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X83Y366        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y366        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.228 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]/Q
                         net (fo=2, routed)           0.043     2.271    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[3]_0[3]
    SLICE_X83Y366        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.126     6.386    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X83Y366        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]/C
                         clock pessimism             -4.191     2.196    
    SLICE_X83Y366        FDCE (Hold_CFF2_SLICEM_C_D)
                                                      0.047     2.243    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.243    
                         arrival time                           2.271    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.085ns  (logic 0.039ns (46.054%)  route 0.046ns (53.946%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.391ns
    Source Clock Delay      (SCD):    2.193ns
    Clock Pessimism Removal (CPR):    4.192ns
  Clock Net Delay (Source):      1.000ns (routing 0.294ns, distribution 0.706ns)
  Clock Net Delay (Destination): 1.131ns (routing 0.330ns, distribution 0.801ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.000     2.193    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/m_bscan_tck[0]
    SLICE_X83Y364        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y364        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.232 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[3]/Q
                         net (fo=2, routed)           0.046     2.278    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/fifo_din[2]
    SLICE_X83Y364        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.131     6.391    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/m_bscan_tck[0]
    SLICE_X83Y364        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[2]/C
                         clock pessimism             -4.192     2.199    
    SLICE_X83Y364        FDCE (Hold_CFF2_SLICEM_C_D)
                                                      0.047     2.246    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_reg_in_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.246    
                         arrival time                           2.278    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.133ns  (logic 0.060ns (45.212%)  route 0.073ns (54.788%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.514ns
    Source Clock Delay      (SCD):    3.033ns
    Clock Pessimism Removal (CPR):    4.443ns
  Clock Net Delay (Source):      1.632ns (routing 0.483ns, distribution 1.149ns)
  Clock Net Delay (Destination): 1.849ns (routing 0.533ns, distribution 1.316ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.632     3.033    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X101Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y333       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     3.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/Q
                         net (fo=5, routed)           0.073     3.165    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp_reg_0
    SLICE_X101Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.849     7.514    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X101Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp_reg/C
                         clock pessimism             -4.443     3.071    
    SLICE_X101Y334       FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     3.133    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/icn_cmd_en_temp_reg
  -------------------------------------------------------------------
                         required time                         -3.133    
                         arrival time                           3.165    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.060ns (44.212%)  route 0.076ns (55.788%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.514ns
    Source Clock Delay      (SCD):    3.033ns
    Clock Pessimism Removal (CPR):    4.443ns
  Clock Net Delay (Source):      1.632ns (routing 0.483ns, distribution 1.149ns)
  Clock Net Delay (Destination): 1.849ns (routing 0.533ns, distribution 1.316ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.632     3.033    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X101Y333       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y333       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     3.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[7]/Q
                         net (fo=5, routed)           0.076     3.168    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg_0
    SLICE_X101Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.849     7.514    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X101Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/C
                         clock pessimism             -4.443     3.071    
    SLICE_X101Y334       FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     3.133    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg
  -------------------------------------------------------------------
                         required time                         -3.133    
                         arrival time                           3.168    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_din_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_din_temp_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.059ns (42.939%)  route 0.078ns (57.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.037ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.514ns
    Source Clock Delay      (SCD):    3.034ns
    Clock Pessimism Removal (CPR):    4.443ns
  Clock Net Delay (Source):      1.633ns (routing 0.483ns, distribution 1.150ns)
  Clock Net Delay (Destination): 1.849ns (routing 0.533ns, distribution 1.316ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.633     3.034    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X101Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_din_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y332       FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.093 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_din_reg/Q
                         net (fo=11, routed)          0.078     3.171    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_din_temp_reg_0[0]
    SLICE_X101Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_din_temp_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.849     7.514    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X101Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_din_temp_reg/C
                         clock pessimism             -4.443     3.071    
    SLICE_X101Y334       FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.062     3.133    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_din_temp_reg
  -------------------------------------------------------------------
                         required time                         -3.133    
                         arrival time                           3.171    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.037ns (40.356%)  route 0.055ns (59.644%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.395ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    4.192ns
  Clock Net Delay (Source):      1.005ns (routing 0.294ns, distribution 0.711ns)
  Clock Net Delay (Destination): 1.135ns (routing 0.330ns, distribution 0.805ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.005     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y366        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.235 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/Q
                         net (fo=2, routed)           0.055     2.289    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[7]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.135     6.395    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/C
                         clock pessimism             -4.192     2.204    
    SLICE_X89Y366        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.046     2.250    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.250    
                         arrival time                           2.289    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.042ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.038ns (36.300%)  route 0.067ns (63.700%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.392ns
    Source Clock Delay      (SCD):    2.199ns
    Clock Pessimism Removal (CPR):    4.178ns
  Clock Net Delay (Source):      1.006ns (routing 0.294ns, distribution 0.712ns)
  Clock Net Delay (Destination): 1.132ns (routing 0.330ns, distribution 0.802ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.006     2.199    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y366        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[2]/Q
                         net (fo=2, routed)           0.067     2.303    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[2]
    SLICE_X89Y367        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.132     6.392    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y367        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]/C
                         clock pessimism             -4.178     2.214    
    SLICE_X89Y367        FDRE (Hold_BFF2_SLICEM_C_D)
                                                      0.047     2.261    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.261    
                         arrival time                           2.303    
  -------------------------------------------------------------------
                         slack                                  0.042    

Slack (MET) :             0.042ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.102ns  (logic 0.038ns (37.371%)  route 0.064ns (62.629%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.395ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    4.185ns
  Clock Net Delay (Source):      1.005ns (routing 0.294ns, distribution 0.711ns)
  Clock Net Delay (Destination): 1.135ns (routing 0.330ns, distribution 0.805ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.005     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y372        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/Q
                         net (fo=2, routed)           0.064     2.299    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[6]
    SLICE_X90Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.135     6.395    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[5]/C
                         clock pessimism             -4.185     2.210    
    SLICE_X90Y372        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.047     2.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.257    
                         arrival time                           2.299    
  -------------------------------------------------------------------
                         slack                                  0.042    

Slack (MET) :             0.043ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.222%)  route 0.066ns (62.778%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.403ns
    Source Clock Delay      (SCD):    2.208ns
    Clock Pessimism Removal (CPR):    4.180ns
  Clock Net Delay (Source):      1.015ns (routing 0.294ns, distribution 0.721ns)
  Clock Net Delay (Destination): 1.143ns (routing 0.330ns, distribution 0.813ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.015     2.208    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y332       FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.247 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/Q
                         net (fo=4, routed)           0.066     2.312    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iCORE_ID[0]
    SLICE_X101Y331       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.143     6.403    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y331       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism             -4.180     2.223    
    SLICE_X101Y331       FDCE (Hold_EFF2_SLICEL_C_D)
                                                      0.047     2.270    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         -2.270    
                         arrival time                           2.312    
  -------------------------------------------------------------------
                         slack                                  0.043    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
Waveform(ns):       { 0.000 25.000 }
Period(ns):         50.000
Sources:            { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I    n/a            1.290         50.000      48.710     BUFGCE_X0Y49   dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X83Y363  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  sys_clk_ddr4_clk_p

Setup :            0  Failing Endpoints,  Worst Slack        1.761ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.050ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.761ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/S
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.387ns  (logic 0.081ns (5.838%)  route 1.306ns (94.162%))
  Logic Levels:           0  
  Clock Path Skew:        -0.077ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.909ns = ( 5.243 - 3.334 ) 
    Source Clock Delay      (SCD):    2.227ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.141ns (routing 0.171ns, distribution 0.970ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.141     2.227    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y351        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.308 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.306     3.614    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/S
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.994     5.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism              0.241     5.484    
                         clock uncertainty           -0.035     5.449    
    SLICE_X81Y323        FDSE (Setup_BFF_SLICEL_C_S)
                                                     -0.074     5.375    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                          5.375    
                         arrival time                          -3.614    
  -------------------------------------------------------------------
                         slack                                  1.761    

Slack (MET) :             1.761ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/S
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.387ns  (logic 0.081ns (5.838%)  route 1.306ns (94.162%))
  Logic Levels:           0  
  Clock Path Skew:        -0.077ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.909ns = ( 5.243 - 3.334 ) 
    Source Clock Delay      (SCD):    2.227ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.141ns (routing 0.171ns, distribution 0.970ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.141     2.227    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y351        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.308 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.306     3.614    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/S
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.994     5.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism              0.241     5.484    
                         clock uncertainty           -0.035     5.449    
    SLICE_X81Y323        FDSE (Setup_DFF_SLICEL_C_S)
                                                     -0.074     5.375    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                          5.375    
                         arrival time                          -3.614    
  -------------------------------------------------------------------
                         slack                                  1.761    

Slack (MET) :             1.761ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/S
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.387ns  (logic 0.081ns (5.838%)  route 1.306ns (94.162%))
  Logic Levels:           0  
  Clock Path Skew:        -0.077ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.909ns = ( 5.243 - 3.334 ) 
    Source Clock Delay      (SCD):    2.227ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.141ns (routing 0.171ns, distribution 0.970ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.141     2.227    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y351        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.308 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/Q
                         net (fo=4, routed)           1.306     3.614    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[3]
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/S
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.994     5.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism              0.241     5.484    
                         clock uncertainty           -0.035     5.449    
    SLICE_X81Y323        FDSE (Setup_DFF2_SLICEL_C_S)
                                                     -0.074     5.375    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                          5.375    
                         arrival time                          -3.614    
  -------------------------------------------------------------------
                         slack                                  1.761    

Slack (MET) :             1.953ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.252ns  (logic 0.328ns (26.206%)  route 0.924ns (73.794%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.909ns = ( 5.243 - 3.334 ) 
    Source Clock Delay      (SCD):    2.228ns
    Clock Pessimism Removal (CPR):    0.300ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.142ns (routing 0.171ns, distribution 0.971ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.142     2.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y324        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.309 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.593     2.902    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y324        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     3.025 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.057     3.082    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y323        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.124     3.206 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.273     3.480    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.994     5.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.300     5.542    
                         clock uncertainty           -0.035     5.507    
    SLICE_X81Y324        FDRE (Setup_EFF_SLICEL_C_R)
                                                     -0.074     5.433    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          5.433    
                         arrival time                          -3.480    
  -------------------------------------------------------------------
                         slack                                  1.953    

Slack (MET) :             1.964ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.253ns  (logic 0.328ns (26.186%)  route 0.925ns (73.814%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.907ns = ( 5.241 - 3.334 ) 
    Source Clock Delay      (SCD):    2.228ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.142ns (routing 0.171ns, distribution 0.971ns)
  Clock Net Delay (Destination): 0.992ns (routing 0.155ns, distribution 0.837ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.142     2.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y324        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.309 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.593     2.902    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y324        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     3.025 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.057     3.082    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y323        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.124     3.206 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.274     3.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.992     5.241    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                         clock pessimism              0.313     5.554    
                         clock uncertainty           -0.035     5.519    
    SLICE_X81Y324        FDRE (Setup_BFF2_SLICEL_C_R)
                                                     -0.074     5.445    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]
  -------------------------------------------------------------------
                         required time                          5.445    
                         arrival time                          -3.481    
  -------------------------------------------------------------------
                         slack                                  1.964    

Slack (MET) :             1.964ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.253ns  (logic 0.328ns (26.186%)  route 0.925ns (73.814%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.907ns = ( 5.241 - 3.334 ) 
    Source Clock Delay      (SCD):    2.228ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.142ns (routing 0.171ns, distribution 0.971ns)
  Clock Net Delay (Destination): 0.992ns (routing 0.155ns, distribution 0.837ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.142     2.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y324        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.309 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.593     2.902    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y324        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     3.025 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.057     3.082    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y323        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.124     3.206 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.274     3.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.992     5.241    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism              0.313     5.554    
                         clock uncertainty           -0.035     5.519    
    SLICE_X81Y324        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.074     5.445    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                          5.445    
                         arrival time                          -3.481    
  -------------------------------------------------------------------
                         slack                                  1.964    

Slack (MET) :             1.964ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.253ns  (logic 0.328ns (26.186%)  route 0.925ns (73.814%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.008ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.907ns = ( 5.241 - 3.334 ) 
    Source Clock Delay      (SCD):    2.228ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.142ns (routing 0.171ns, distribution 0.971ns)
  Clock Net Delay (Destination): 0.992ns (routing 0.155ns, distribution 0.837ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.142     2.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y324        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.309 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.593     2.902    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y324        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     3.025 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.057     3.082    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y323        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.124     3.206 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.274     3.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.992     5.241    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism              0.313     5.554    
                         clock uncertainty           -0.035     5.519    
    SLICE_X81Y324        FDRE (Setup_DFF2_SLICEL_C_R)
                                                     -0.074     5.445    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                          5.445    
                         arrival time                          -3.481    
  -------------------------------------------------------------------
                         slack                                  1.964    

Slack (MET) :             1.985ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.319ns  (logic 0.300ns (22.743%)  route 1.019ns (77.257%))
  Logic Levels:           2  (LUT4=2)
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.909ns = ( 5.243 - 3.334 ) 
    Source Clock Delay      (SCD):    2.228ns
    Clock Pessimism Removal (CPR):    0.300ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.142ns (routing 0.171ns, distribution 0.971ns)
  Clock Net Delay (Destination): 0.994ns (routing 0.155ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.142     2.228    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y324        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.309 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/Q
                         net (fo=3, routed)           0.593     2.902    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]
    SLICE_X81Y324        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     3.025 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.099     3.124    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X81Y323        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.220 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_2/O
                         net (fo=1, routed)           0.327     3.547    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[6]
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.994     5.243    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.300     5.542    
                         clock uncertainty           -0.035     5.507    
    SLICE_X81Y324        FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.025     5.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          5.532    
                         arrival time                          -3.547    
  -------------------------------------------------------------------
                         slack                                  1.985    

Slack (MET) :             2.044ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.239ns  (logic 0.241ns (19.451%)  route 0.998ns (80.549%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.041ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.953ns = ( 5.287 - 3.334 ) 
    Source Clock Delay      (SCD):    2.235ns
    Clock Pessimism Removal (CPR):    0.241ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.149ns (routing 0.171ns, distribution 0.978ns)
  Clock Net Delay (Destination): 1.038ns (routing 0.155ns, distribution 0.883ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.149     2.235    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.315 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/Q
                         net (fo=2, routed)           0.196     2.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design
    SLICE_X81Y323        LUT3 (Prop_A5LUT_SLICEL_I1_O)
                                                      0.161     2.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.802     3.474    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.038     5.287    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                         clock pessimism              0.241     5.528    
                         clock uncertainty           -0.035     5.493    
    SLICE_X96Y320        FDRE (Setup_AFF2_SLICEM_C_D)
                                                      0.025     5.518    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg
  -------------------------------------------------------------------
                         required time                          5.518    
                         arrival time                          -3.474    
  -------------------------------------------------------------------
                         slack                                  2.044    

Slack (MET) :             2.186ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (sys_clk_ddr4_clk_p rise@3.334ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        1.103ns  (logic 0.327ns (29.634%)  route 0.776ns (70.366%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.905ns = ( 5.239 - 3.334 ) 
    Source Clock Delay      (SCD):    2.230ns
    Clock Pessimism Removal (CPR):    0.291ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.144ns (routing 0.171ns, distribution 0.973ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.155ns, distribution 0.835ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.144     2.230    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDSE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.311 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/Q
                         net (fo=7, routed)           0.249     2.561    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]
    SLICE_X81Y323        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.136     2.697 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2/O
                         net (fo=1, routed)           0.253     2.950    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2_n_0
    SLICE_X81Y324        LUT5 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.110     3.060 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1/O
                         net (fo=1, routed)           0.274     3.334    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1_n_0
    SLICE_X81Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      3.334     3.334 r  
    J19                                               0.000     3.334 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.888 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.928    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.928 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     4.225    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.249 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.990     5.239    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/C
                         clock pessimism              0.291     5.530    
                         clock uncertainty           -0.035     5.495    
    SLICE_X81Y322        FDRE (Setup_AFF2_SLICEL_C_D)
                                                      0.025     5.520    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg
  -------------------------------------------------------------------
                         required time                          5.520    
                         arrival time                          -3.334    
  -------------------------------------------------------------------
                         slack                                  2.186    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.050ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.103ns  (logic 0.072ns (70.006%)  route 0.031ns (29.994%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.528ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.649ns (routing 0.096ns, distribution 0.553ns)
  Clock Net Delay (Destination): 0.741ns (routing 0.108ns, distribution 0.633ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.649     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y324        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.305 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.025     1.329    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X81Y324        LUT4 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     1.362 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]_i_1/O
                         net (fo=1, routed)           0.006     1.368    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[3]
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.741     1.528    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism             -0.256     1.272    
    SLICE_X81Y324        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.319    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.319    
                         arrival time                           1.368    
  -------------------------------------------------------------------
                         slack                                  0.050    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.062ns (59.798%)  route 0.042ns (40.202%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.267ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.650ns (routing 0.096ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.650     1.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.306 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           0.027     1.332    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X81Y323        LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.023     1.355 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.015     1.370    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism             -0.256     1.273    
    SLICE_X81Y323        FDSE (Hold_BFF_SLICEL_C_D)
                                                      0.046     1.319    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.319    
                         arrival time                           1.370    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.072ns (68.771%)  route 0.033ns (31.229%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.267ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.650ns (routing 0.096ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.650     1.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.306 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.027     1.332    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X81Y323        LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.033     1.365 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1/O
                         net (fo=1, routed)           0.006     1.371    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1_n_0
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism             -0.256     1.273    
    SLICE_X81Y323        FDSE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.320    
                         arrival time                           1.371    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.119ns  (logic 0.059ns (49.567%)  route 0.060ns (50.433%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.533ns
    Source Clock Delay      (SCD):    1.269ns
    Clock Pessimism Removal (CPR):    0.245ns
  Clock Net Delay (Source):      0.652ns (routing 0.096ns, distribution 0.556ns)
  Clock Net Delay (Destination): 0.746ns (routing 0.108ns, distribution 0.638ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.652     1.269    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y324        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.308 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/Q
                         net (fo=7, routed)           0.054     1.362    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]
    SLICE_X81Y323        LUT4 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.020     1.382 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1/O
                         net (fo=1, routed)           0.006     1.388    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1_n_0
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.746     1.533    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                         clock pessimism             -0.245     1.288    
    SLICE_X81Y323        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.335    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg
  -------------------------------------------------------------------
                         required time                         -1.335    
                         arrival time                           1.388    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.063ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.115ns  (logic 0.074ns (64.433%)  route 0.041ns (35.567%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.528ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.649ns (routing 0.096ns, distribution 0.553ns)
  Clock Net Delay (Destination): 0.741ns (routing 0.108ns, distribution 0.633ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.649     1.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y324        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.305 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.025     1.329    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X81Y324        LUT3 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.364 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]_i_1/O
                         net (fo=1, routed)           0.016     1.380    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[2]
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.741     1.528    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism             -0.256     1.272    
    SLICE_X81Y324        FDRE (Hold_DFF_SLICEL_C_D)
                                                      0.046     1.318    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.318    
                         arrival time                           1.380    
  -------------------------------------------------------------------
                         slack                                  0.063    

Slack (MET) :             0.065ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
                            (rising edge-triggered cell FDSE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.117ns  (logic 0.074ns (63.413%)  route 0.043ns (36.587%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.267ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.650ns (routing 0.096ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.650     1.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y323        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.306 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.027     1.332    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X81Y323        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.367 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1/O
                         net (fo=1, routed)           0.016     1.383    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1_n_0
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y323        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism             -0.256     1.273    
    SLICE_X81Y323        FDSE (Hold_DFF_SLICEL_C_D)
                                                      0.046     1.319    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.319    
                         arrival time                           1.383    
  -------------------------------------------------------------------
                         slack                                  0.065    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.267ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.650ns (routing 0.096ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.650     1.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y351        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.307 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/Q
                         net (fo=1, routed)           0.081     1.388    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[0]
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                         clock pessimism             -0.256     1.273    
    SLICE_X81Y351        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.320    
                         arrival time                           1.388    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.787%)  route 0.082ns (67.213%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.267ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.650ns (routing 0.096ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.650     1.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y351        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.307 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/Q
                         net (fo=1, routed)           0.082     1.389    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[2]
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                         clock pessimism             -0.256     1.273    
    SLICE_X81Y351        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.320    
                         arrival time                           1.389    
  -------------------------------------------------------------------
                         slack                                  0.069    

Slack (MET) :             0.086ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
                            (rising edge-triggered cell FDPE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.139ns  (logic 0.040ns (28.777%)  route 0.099ns (71.223%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.267ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.650ns (routing 0.096ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.650     1.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y350        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y350        FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.307 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/Q
                         net (fo=1, routed)           0.099     1.406    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[0]
    SLICE_X81Y350        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y350        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                         clock pessimism             -0.256     1.273    
    SLICE_X81Y350        FDPE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.320    
                         arrival time                           1.406    
  -------------------------------------------------------------------
                         slack                                  0.086    

Slack (MET) :             0.087ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             sys_clk_ddr4_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (sys_clk_ddr4_clk_p rise@0.000ns - sys_clk_ddr4_clk_p rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.040ns (28.571%)  route 0.100ns (71.429%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.267ns
    Clock Pessimism Removal (CPR):    0.256ns
  Clock Net Delay (Source):      0.650ns (routing 0.096ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.650     1.267    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y351        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.307 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/Q
                         net (fo=1, routed)           0.100     1.407    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[1]
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                         clock pessimism             -0.256     1.273    
    SLICE_X81Y351        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.047     1.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.320    
                         arrival time                           1.407    
  -------------------------------------------------------------------
                         slack                                  0.087    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         sys_clk_ddr4_clk_p
Waveform(ns):       { 0.000 1.667 }
Period(ns):         3.334
Sources:            { sys_clk_ddr4_clk_p }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I           n/a            1.290         3.334       2.044      BUFGCE_X0Y138  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.334       2.263      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y323  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y323  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X81Y323  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X81Y323  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.334       96.666     MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y323  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y323  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y323  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X81Y323  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X81Y324  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Setup :            1  Failing Endpoint ,  Worst Slack       -0.011ns,  Total Violation       -0.011ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -0.011ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.965ns  (logic 0.725ns (24.452%)  route 2.240ns (75.548%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.363ns = ( 7.364 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.216ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.729ns (routing 0.632ns, distribution 1.097ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.049     5.910    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X91Y260        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     5.946 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.442     6.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X89Y288        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.037     6.424 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_2__0/O
                         net (fo=30, routed)          0.507     6.932    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_2__0_n_0
    SLICE_X87Y328        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     7.055 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[0]_i_1__0/O
                         net (fo=1, routed)           0.066     7.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[0]_i_1__0_n_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.729     7.364    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                         clock pessimism             -0.216     7.147    
                         clock uncertainty           -0.062     7.085    
    SLICE_X87Y328        FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     7.110    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]
  -------------------------------------------------------------------
                         required time                          7.110    
                         arrival time                          -7.121    
  -------------------------------------------------------------------
                         slack                                 -0.011    

Slack (MET) :             0.016ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[39]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.870ns  (logic 0.747ns (26.029%)  route 2.123ns (73.971%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.077ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.381ns = ( 7.382 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.303ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.747ns (routing 0.632ns, distribution 1.115ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.049     5.910    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X91Y260        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     5.946 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.442     6.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X89Y288        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.037     6.424 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_2__0/O
                         net (fo=30, routed)          0.390     6.815    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_2__0_n_0
    SLICE_X90Y304        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.145     6.960 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[39]_i_1__0/O
                         net (fo=1, routed)           0.066     7.026    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[39]_i_1__0_n_0
    SLICE_X90Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[39]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.747     7.382    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X90Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[39]/C
                         clock pessimism             -0.303     7.079    
                         clock uncertainty           -0.062     7.017    
    SLICE_X90Y304        FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     7.042    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[39]
  -------------------------------------------------------------------
                         required time                          7.042    
                         arrival time                          -7.026    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.026ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.888ns  (logic 0.742ns (25.692%)  route 2.146ns (74.308%))
  Logic Levels:           8  (CARRY8=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.410ns = ( 7.411 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.303ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.776ns (routing 0.632ns, distribution 1.144ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.049     5.910    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X91Y260        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     5.946 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.773     6.719    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X89Y318        LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.052     6.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[30]_i_2__0/O
                         net (fo=1, routed)           0.095     6.866    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[30]_i_2__0_n_0
    SLICE_X89Y319        LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.125     6.991 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[30]_i_1__0/O
                         net (fo=1, routed)           0.053     7.044    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[30]_i_1__0_n_0
    SLICE_X89Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.776     7.411    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X89Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[30]/C
                         clock pessimism             -0.303     7.108    
                         clock uncertainty           -0.062     7.045    
    SLICE_X89Y319        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025     7.070    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[30]
  -------------------------------------------------------------------
                         required time                          7.070    
                         arrival time                          -7.044    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.036ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.826ns  (logic 0.690ns (24.414%)  route 2.136ns (75.586%))
  Logic Levels:           7  (CARRY8=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.101ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.358ns = ( 7.358 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.303ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.724ns (routing 0.632ns, distribution 1.092ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.049     5.910    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X91Y260        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     5.946 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.852     6.798    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X86Y323        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.125     6.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_1__0/O
                         net (fo=1, routed)           0.059     6.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_1__0_n_0
    SLICE_X86Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.724     7.358    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X86Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr_reg[1]/C
                         clock pessimism             -0.303     7.055    
                         clock uncertainty           -0.062     6.993    
    SLICE_X86Y323        FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025     7.018    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr_reg[1]
  -------------------------------------------------------------------
                         required time                          7.018    
                         arrival time                          -6.982    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.801ns  (logic 0.655ns (23.387%)  route 2.146ns (76.613%))
  Logic Levels:           7  (CARRY8=1 LUT2=1 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.369ns = ( 7.370 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.735ns (routing 0.632ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.326     6.186    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X88Y271        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.090     6.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[2]_i_5__1/O
                         net (fo=4, routed)           0.501     6.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[2]_i_5__1_n_0
    SLICE_X88Y322        LUT4 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     6.814 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP[1]_i_1__1/O
                         net (fo=3, routed)           0.143     6.957    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP[1]_i_1__1_n_0
    SLICE_X88Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.735     7.370    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X88Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP_reg[0]/C
                         clock pessimism             -0.253     7.117    
                         clock uncertainty           -0.062     7.054    
    SLICE_X88Y322        FDRE (Setup_HFF2_SLICEL_C_CE)
                                                     -0.060     6.994    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP_reg[0]
  -------------------------------------------------------------------
                         required time                          6.994    
                         arrival time                          -6.957    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP_reg[1]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.801ns  (logic 0.655ns (23.387%)  route 2.146ns (76.613%))
  Logic Levels:           7  (CARRY8=1 LUT2=1 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.369ns = ( 7.370 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.735ns (routing 0.632ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.326     6.186    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X88Y271        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.090     6.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[2]_i_5__1/O
                         net (fo=4, routed)           0.501     6.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[2]_i_5__1_n_0
    SLICE_X88Y322        LUT4 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     6.814 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP[1]_i_1__1/O
                         net (fo=3, routed)           0.143     6.957    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP[1]_i_1__1_n_0
    SLICE_X88Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.735     7.370    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X88Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP_reg[1]/C
                         clock pessimism             -0.253     7.117    
                         clock uncertainty           -0.062     7.054    
    SLICE_X88Y322        FDRE (Setup_GFF2_SLICEL_C_CE)
                                                     -0.060     6.994    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP_reg[1]
  -------------------------------------------------------------------
                         required time                          6.994    
                         arrival time                          -6.957    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.801ns  (logic 0.655ns (23.387%)  route 2.146ns (76.613%))
  Logic Levels:           7  (CARRY8=1 LUT2=1 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.369ns = ( 7.370 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.735ns (routing 0.632ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.326     6.186    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X88Y271        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.090     6.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[2]_i_5__1/O
                         net (fo=4, routed)           0.501     6.778    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[2]_i_5__1_n_0
    SLICE_X88Y322        LUT4 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.036     6.814 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP[1]_i_1__1/O
                         net (fo=3, routed)           0.143     6.957    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdBankP[1]_i_1__1_n_0
    SLICE_X88Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.735     7.370    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X88Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]/C
                         clock pessimism             -0.253     7.117    
                         clock uncertainty           -0.062     7.054    
    SLICE_X88Y322        FDRE (Setup_FFF2_SLICEL_C_CE)
                                                     -0.060     6.994    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]
  -------------------------------------------------------------------
                         required time                          6.994    
                         arrival time                          -6.957    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.046ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.829ns  (logic 0.745ns (26.336%)  route 2.084ns (73.664%))
  Logic Levels:           8  (CARRY8=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.089ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.370ns = ( 7.371 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.303ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.736ns (routing 0.632ns, distribution 1.104ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.049     5.910    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X91Y260        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     5.946 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.504     6.450    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X88Y286        LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.090     6.540 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[27]_i_2__0/O
                         net (fo=1, routed)           0.302     6.842    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[27]_i_2__0_n_0
    SLICE_X89Y304        LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.090     6.932 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[27]_i_1__0/O
                         net (fo=1, routed)           0.053     6.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[27]_i_1__0_n_0
    SLICE_X89Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.736     7.371    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X89Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[27]/C
                         clock pessimism             -0.303     7.068    
                         clock uncertainty           -0.062     7.005    
    SLICE_X89Y304        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025     7.030    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[27]
  -------------------------------------------------------------------
                         required time                          7.030    
                         arrival time                          -6.985    
  -------------------------------------------------------------------
                         slack                                  0.046    

Slack (MET) :             0.048ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.831ns  (logic 0.752ns (26.559%)  route 2.079ns (73.441%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.375ns = ( 7.375 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.303ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.741ns (routing 0.632ns, distribution 1.109ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.049     5.910    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X91Y260        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     5.946 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.442     6.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X89Y288        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.037     6.424 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_2__0/O
                         net (fo=30, routed)          0.360     6.784    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[47]_i_2__0_n_0
    SLICE_X89Y301        LUT6 (Prop_A6LUT_SLICEM_I5_O)
                                                      0.150     6.934 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[25]_i_1__0/O
                         net (fo=1, routed)           0.053     6.987    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output[25]_i_1__0_n_0
    SLICE_X89Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.741     7.375    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X89Y301        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[25]/C
                         clock pessimism             -0.303     7.072    
                         clock uncertainty           -0.062     7.010    
    SLICE_X89Y301        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025     7.035    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[25]
  -------------------------------------------------------------------
                         required time                          7.035    
                         arrival time                          -6.987    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.054ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_gr_cas_state_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.867ns  (logic 0.651ns (22.708%)  route 2.216ns (77.292%))
  Logic Levels:           8  (CARRY8=1 LUT5=3 LUT6=4)
  Clock Path Skew:        -0.043ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.366ns = ( 7.367 - 3.001 ) 
    Source Clock Delay      (SCD):    4.156ns
    Clock Pessimism Removal (CPR):    -0.253ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.960ns (routing 0.696ns, distribution 1.264ns)
  Clock Net Delay (Destination): 1.732ns (routing 0.632ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.960     4.156    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X87Y328        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y328        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.450     4.684    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/Q[0]
    SLICE_X90Y299        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.088     4.772 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2/O
                         net (fo=1, routed)           0.505     5.277    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_19__2_n_0
    SLICE_X92Y260        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.098     5.375 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2/O
                         net (fo=1, routed)           0.009     5.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/i__carry_i_5__2_n_0
    SLICE_X92Y260        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     5.579 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.172     5.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X91Y260        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.035     5.786 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6/O
                         net (fo=1, routed)           0.040     5.826    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6_n_0
    SLICE_X91Y260        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     5.861 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0/O
                         net (fo=4, routed)           0.049     5.910    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_grSt[1]_i_3__0_n_0
    SLICE_X91Y260        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     5.946 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0/O
                         net (fo=75, routed)          0.673     6.619    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__0_n_0
    SLICE_X91Y312        LUT5 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.050     6.669 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_gr_cas_state[2]_i_5/O
                         net (fo=4, routed)           0.269     6.938    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_gr_cas_state[2]_i_5_n_0
    SLICE_X88Y323        LUT5 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     6.974 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_gr_cas_state[2]_i_2__2/O
                         net (fo=1, routed)           0.049     7.023    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/gr_cas_state_nxt[2]
    SLICE_X88Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_gr_cas_state_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.732     7.367    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/cmdGroupP_reg[0]_0
    SLICE_X88Y323        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_gr_cas_state_reg[2]/C
                         clock pessimism             -0.253     7.114    
                         clock uncertainty           -0.062     7.052    
    SLICE_X88Y323        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025     7.077    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[3].u_ddr_mc_group/FSM_sequential_gr_cas_state_reg[2]
  -------------------------------------------------------------------
                         required time                          7.077    
                         arrival time                          -7.023    
  -------------------------------------------------------------------
                         slack                                  0.054    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][435]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[627].srl_nx1/shift_reg_reg[0]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.625%)  route 0.057ns (59.375%))
  Logic Levels:           0  
  Clock Path Skew:        0.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.550ns
    Source Clock Delay      (SCD):    2.650ns
    Clock Pessimism Removal (CPR):    -0.139ns
  Clock Net Delay (Source):      1.103ns (routing 0.385ns, distribution 0.718ns)
  Clock Net Delay (Destination): 1.267ns (routing 0.432ns, distribution 0.835ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.103     2.650    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/aclk
    SLICE_X107Y143       FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][435]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y143       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.689 r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][435]/Q
                         net (fo=2, routed)           0.057     2.746    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[627].srl_nx1/s_mesg[0]
    SLICE_X107Y144       SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[627].srl_nx1/shift_reg_reg[0]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.267     2.550    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[627].srl_nx1/aclk
    SLICE_X107Y144       SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[627].srl_nx1/shift_reg_reg[0]_srl32/CLK
                         clock pessimism              0.139     2.689    
    SLICE_X107Y144       SRLC32E (Hold_C6LUT_SLICEM_CLK_D)
                                                      0.046     2.735    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[627].srl_nx1/shift_reg_reg[0]_srl32
  -------------------------------------------------------------------
                         required time                         -2.735    
                         arrival time                           2.746    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[468]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1493]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.201ns  (logic 0.058ns (28.880%)  route 0.143ns (71.120%))
  Logic Levels:           0  
  Clock Path Skew:        0.127ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.202ns
    Source Clock Delay      (SCD):    4.427ns
    Clock Pessimism Removal (CPR):    -0.352ns
  Clock Net Delay (Source):      1.793ns (routing 0.632ns, distribution 1.161ns)
  Clock Net Delay (Destination): 2.006ns (routing 0.696ns, distribution 1.310ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.793     4.427    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X105Y118       FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[468]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y118       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     4.485 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[468]/Q
                         net (fo=2, routed)           0.143     4.628    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2112]_0[469]
    SLICE_X106Y120       FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1493]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.006     4.202    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X106Y120       FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1493]/C
                         clock pessimism              0.352     4.554    
    SLICE_X106Y120       FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     4.616    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1493]
  -------------------------------------------------------------------
                         required time                         -4.616    
                         arrival time                           4.628    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0/RAMB_D1/I
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.059ns (32.940%)  route 0.120ns (67.060%))
  Logic Levels:           0  
  Clock Path Skew:        0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.138ns
    Source Clock Delay      (SCD):    4.339ns
    Clock Pessimism Removal (CPR):    -0.309ns
  Clock Net Delay (Source):      1.705ns (routing 0.632ns, distribution 1.073ns)
  Clock Net Delay (Destination): 1.942ns (routing 0.696ns, distribution 1.246ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.705     4.339    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y288        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y288        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.398 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/rdData_reg[9]/Q
                         net (fo=3, routed)           0.120     4.518    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0/DIB1
    SLICE_X82Y289        RAMD32                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0/RAMB_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.942     4.138    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0/WCLK
    SLICE_X82Y289        RAMD32                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0/RAMB_D1/CLK
                         clock pessimism              0.309     4.447    
    SLICE_X82Y289        RAMD32 (Hold_F6LUT_SLICEM_CLK_I)
                                                      0.060     4.507    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf.rd_buffer_ram[1].RAM32M0/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -4.507    
                         arrival time                           4.518    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[62]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
                            (rising edge-triggered cell RXTX_BITSLICE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.189ns  (logic 0.040ns (21.164%)  route 0.149ns (78.836%))
  Logic Levels:           0  
  Clock Path Skew:        0.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.567ns
    Source Clock Delay      (SCD):    2.582ns
    Clock Pessimism Removal (CPR):    -0.150ns
  Clock Net Delay (Source):      1.035ns (routing 0.385ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.285ns (routing 0.432ns, distribution 0.853ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.035     2.582    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y236        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[62]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y236        FDSE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.622 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[62]/Q
                         net (fo=1, routed)           0.149     2.771    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_clb2phy_fifo_rden[0]
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.285     2.567    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/div_clk
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
                         clock pessimism              0.150     2.718    
    BITSLICE_RX_TX_X0Y205
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_FIFO_RD_CLK_FIFO_RD_EN)
                                                      0.041     2.759    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.759    
                         arrival time                           2.771    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][26]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[218].srl_nx1/shift_reg_reg[0]_srl32/D
                            (rising edge-triggered cell SRLC32E clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.669%)  route 0.059ns (60.332%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.540ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.140ns
  Clock Net Delay (Source):      1.095ns (routing 0.385ns, distribution 0.710ns)
  Clock Net Delay (Destination): 1.257ns (routing 0.432ns, distribution 0.825ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.095     2.642    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/aclk
    SLICE_X98Y139        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y139        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.681 r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][26]/Q
                         net (fo=2, routed)           0.059     2.740    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[218].srl_nx1/s_mesg[0]
    SLICE_X97Y139        SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[218].srl_nx1/shift_reg_reg[0]_srl32/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.257     2.540    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[218].srl_nx1/aclk
    SLICE_X97Y139        SRLC32E                                      r  d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[218].srl_nx1/shift_reg_reg[0]_srl32/CLK
                         clock pessimism              0.140     2.679    
    SLICE_X97Y139        SRLC32E (Hold_D6LUT_SLICEM_CLK_D)
                                                      0.046     2.725    d_1_i/ddr4/axi_smc_1/inst/s01_entry_pipeline/s01_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/gen_srls[218].srl_nx1/shift_reg_reg[0]_srl32
  -------------------------------------------------------------------
                         required time                         -2.725    
                         arrival time                           2.740    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.059ns (36.826%)  route 0.101ns (63.174%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.254ns
    Source Clock Delay      (SCD):    4.443ns
    Clock Pessimism Removal (CPR):    -0.247ns
  Clock Net Delay (Source):      1.809ns (routing 0.632ns, distribution 1.177ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.696ns, distribution 1.362ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.809     4.443    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X116Y168       FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y168       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.502 r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.101     4.604    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.058     4.254    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/CLK
                         clock pessimism              0.247     4.500    
    SLICE_X115Y167       RAMD32 (Hold_A5LUT_SLICEM_CLK_WADR1)
                                                      0.088     4.588    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA
  -------------------------------------------------------------------
                         required time                         -4.588    
                         arrival time                           4.604    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.059ns (36.826%)  route 0.101ns (63.174%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.254ns
    Source Clock Delay      (SCD):    4.443ns
    Clock Pessimism Removal (CPR):    -0.247ns
  Clock Net Delay (Source):      1.809ns (routing 0.632ns, distribution 1.177ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.696ns, distribution 1.362ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.809     4.443    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X116Y168       FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y168       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.502 r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.101     4.604    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.058     4.254    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1/CLK
                         clock pessimism              0.247     4.500    
    SLICE_X115Y167       RAMD32 (Hold_A6LUT_SLICEM_CLK_WADR1)
                                                      0.088     4.588    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA_D1
  -------------------------------------------------------------------
                         required time                         -4.588    
                         arrival time                           4.604    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.059ns (36.826%)  route 0.101ns (63.174%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.254ns
    Source Clock Delay      (SCD):    4.443ns
    Clock Pessimism Removal (CPR):    -0.247ns
  Clock Net Delay (Source):      1.809ns (routing 0.632ns, distribution 1.177ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.696ns, distribution 1.362ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.809     4.443    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X116Y168       FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y168       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.502 r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.101     4.604    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.058     4.254    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/CLK
                         clock pessimism              0.247     4.500    
    SLICE_X115Y167       RAMD32 (Hold_B5LUT_SLICEM_CLK_WADR1)
                                                      0.088     4.588    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB
  -------------------------------------------------------------------
                         required time                         -4.588    
                         arrival time                           4.604    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.059ns (36.826%)  route 0.101ns (63.174%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.254ns
    Source Clock Delay      (SCD):    4.443ns
    Clock Pessimism Removal (CPR):    -0.247ns
  Clock Net Delay (Source):      1.809ns (routing 0.632ns, distribution 1.177ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.696ns, distribution 1.362ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.809     4.443    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X116Y168       FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y168       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.502 r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.101     4.604    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.058     4.254    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1/CLK
                         clock pessimism              0.247     4.500    
    SLICE_X115Y167       RAMD32 (Hold_B6LUT_SLICEM_CLK_WADR1)
                                                      0.088     4.588    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB_D1
  -------------------------------------------------------------------
                         required time                         -4.588    
                         arrival time                           4.604    
  -------------------------------------------------------------------
                         slack                                  0.015    

Slack (MET) :             0.015ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC/WADR1
                            (rising edge-triggered cell RAMD32 clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.059ns (36.826%)  route 0.101ns (63.174%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.254ns
    Source Clock Delay      (SCD):    4.443ns
    Clock Pessimism Removal (CPR):    -0.247ns
  Clock Net Delay (Source):      1.809ns (routing 0.632ns, distribution 1.177ns)
  Clock Net Delay (Destination): 2.058ns (routing 0.696ns, distribution 1.362ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.809     4.443    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk
    SLICE_X116Y168       FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X116Y168       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.502 r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[1]/Q
                         net (fo=22, routed)          0.101     4.604    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/ADDRH1
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC/WADR1
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.058     4.254    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X115Y167       RAMD32                                       r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC/CLK
                         clock pessimism              0.247     4.500    
    SLICE_X115Y167       RAMD32 (Hold_C5LUT_SLICEM_CLK_WADR1)
                                                      0.088     4.588    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMC
  -------------------------------------------------------------------
                         required time                         -4.588    
                         arrival time                           4.604    
  -------------------------------------------------------------------
                         slack                                  0.015    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout0
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin                    Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     PS8/MAXIGP1ACLK            n/a            3.000         3.001       0.001      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y162  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y164  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y165  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y166  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0               d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y7               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y8               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y10              d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]
  To Clock:  pll_clk[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y7                d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.316      1.016      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.319      1.019      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.322      1.022      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.323      1.023      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.324      1.024      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.326      1.026      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.471      1.171      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.478      1.178      BITSLICE_CONTROL_X0Y30  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]_DIV
  To Clock:  pll_clk[0]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y162  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y164  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y165  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y166  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y167  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y156  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y158  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y159  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y160  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y161  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]
  To Clock:  pll_clk[1]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y8                d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.308      1.008      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.312      1.012      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.314      1.014      BITSLICE_CONTROL_X0Y37  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.315      1.015      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.315      1.015      BITSLICE_CONTROL_X0Y35  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.316      1.016      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.316      1.016      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.318      1.018      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.458      1.158      BITSLICE_CONTROL_X0Y36  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.466      1.166      BITSLICE_CONTROL_X0Y38  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]_DIV
  To Clock:  pll_clk[1]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y214  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y216  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y217  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y218  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y219  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y208  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y210  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y211  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y212  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y213  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]
  To Clock:  pll_clk[2]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y43  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a            0.333         0.375       0.042      PLL_X0Y10               d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y43  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y42  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[2]_DIV
  To Clock:  pll_clk[2]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[2]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y292  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y293  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y294  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y295  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y296  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y286  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y288  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y289  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y290  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y291  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack        8.333ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.026ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.469ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             8.333ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        3.477ns  (logic 0.308ns (8.859%)  route 3.169ns (91.141%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        -0.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.944ns = ( 15.947 - 12.002 ) 
    Source Clock Delay      (SCD):    3.705ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.518ns (routing 0.635ns, distribution 0.883ns)
  Clock Net Delay (Destination): 1.318ns (routing 0.578ns, distribution 0.740ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.518     3.705    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     3.784 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[1]/Q
                         net (fo=44, routed)          2.537     6.320    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[5]
    SLICE_X81Y351        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     6.370 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_3/O
                         net (fo=1, routed)           0.206     6.576    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_3_n_0
    SLICE_X82Y355        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     6.666 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_2/O
                         net (fo=1, routed)           0.377     7.043    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_2_n_0
    SLICE_X84Y356        LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.089     7.132 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_1/O
                         net (fo=1, routed)           0.049     7.181    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.318    15.947    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/C
                         clock pessimism             -0.382    15.565    
                         clock uncertainty           -0.076    15.489    
    SLICE_X84Y356        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    15.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]
  -------------------------------------------------------------------
                         required time                         15.514    
                         arrival time                          -7.181    
  -------------------------------------------------------------------
                         slack                                  8.333    

Slack (MET) :             8.792ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        3.013ns  (logic 0.347ns (11.518%)  route 2.666ns (88.482%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.147ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.945ns = ( 15.947 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.578ns, distribution 0.741ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     5.705 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.530     6.236    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X81Y355        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     6.286 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]_i_2/O
                         net (fo=1, routed)           0.339     6.625    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]_i_2_n_0
    SLICE_X82Y359        LUT5 (Prop_B5LUT_SLICEM_I0_O)
                                                      0.072     6.697 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]_i_1/O
                         net (fo=1, routed)           0.026     6.723    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[0]
    SLICE_X82Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.319    15.947    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]/C
                         clock pessimism             -0.382    15.565    
                         clock uncertainty           -0.076    15.489    
    SLICE_X82Y359        FDRE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    15.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[0]
  -------------------------------------------------------------------
                         required time                         15.514    
                         arrival time                          -6.723    
  -------------------------------------------------------------------
                         slack                                  8.792    

Slack (MET) :             8.813ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.997ns  (logic 0.350ns (11.677%)  route 2.647ns (88.323%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.142ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.950ns = ( 15.953 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.324ns (routing 0.578ns, distribution 0.746ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     5.705 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.819     6.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X83Y356        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     6.649 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[3]_i_1/O
                         net (fo=1, routed)           0.058     6.707    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[3]
    SLICE_X83Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.324    15.953    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X83Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[3]/C
                         clock pessimism             -0.382    15.571    
                         clock uncertainty           -0.076    15.495    
    SLICE_X83Y356        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025    15.520    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[3]
  -------------------------------------------------------------------
                         required time                         15.520    
                         arrival time                          -6.707    
  -------------------------------------------------------------------
                         slack                                  8.813    

Slack (MET) :             8.950ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.855ns  (logic 0.436ns (15.274%)  route 2.419ns (84.726%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.148ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.944ns = ( 15.947 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.318ns (routing 0.578ns, distribution 0.740ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     5.705 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.415     6.120    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X82Y355        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.123     6.243 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[6]_i_2/O
                         net (fo=1, routed)           0.183     6.426    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[6]_i_2_n_0
    SLICE_X84Y356        LUT5 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.088     6.514 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[6]_i_1/O
                         net (fo=1, routed)           0.050     6.564    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[6]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.318    15.947    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[6]/C
                         clock pessimism             -0.382    15.565    
                         clock uncertainty           -0.076    15.489    
    SLICE_X84Y356        FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.025    15.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[6]
  -------------------------------------------------------------------
                         required time                         15.514    
                         arrival time                          -6.564    
  -------------------------------------------------------------------
                         slack                                  8.950    

Slack (MET) :             8.950ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.855ns  (logic 0.360ns (12.611%)  route 2.495ns (87.389%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.147ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.945ns = ( 15.947 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.578ns, distribution 0.741ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     5.705 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.531     6.237    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X81Y355        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.097     6.334 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[10]_i_3/O
                         net (fo=1, routed)           0.140     6.474    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[10]_i_3_n_0
    SLICE_X82Y357        LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.038     6.512 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[10]_i_1/O
                         net (fo=1, routed)           0.053     6.565    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[10]
    SLICE_X82Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.319    15.947    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[10]/C
                         clock pessimism             -0.382    15.565    
                         clock uncertainty           -0.076    15.489    
    SLICE_X82Y357        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025    15.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[10]
  -------------------------------------------------------------------
                         required time                         15.514    
                         arrival time                          -6.565    
  -------------------------------------------------------------------
                         slack                                  8.950    

Slack (MET) :             8.973ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.832ns  (logic 0.313ns (11.054%)  route 2.519ns (88.946%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.147ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.945ns = ( 15.947 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.578ns, distribution 0.741ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     5.705 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.682     6.388    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X82Y359        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.088     6.476 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_1/O
                         net (fo=1, routed)           0.066     6.542    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]
    SLICE_X82Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.319    15.947    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[15]/C
                         clock pessimism             -0.382    15.565    
                         clock uncertainty           -0.076    15.489    
    SLICE_X82Y359        FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025    15.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[15]
  -------------------------------------------------------------------
                         required time                         15.514    
                         arrival time                          -6.542    
  -------------------------------------------------------------------
                         slack                                  8.973    

Slack (MET) :             9.035ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.766ns  (logic 0.349ns (12.619%)  route 2.417ns (87.381%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.941ns = ( 15.943 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.315ns (routing 0.578ns, distribution 0.737ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     5.705 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.595     6.301    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X81Y359        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     6.425 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[2]_i_1/O
                         net (fo=1, routed)           0.051     6.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[2]
    SLICE_X81Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.315    15.943    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[2]/C
                         clock pessimism             -0.382    15.561    
                         clock uncertainty           -0.076    15.485    
    SLICE_X81Y359        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025    15.510    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[2]
  -------------------------------------------------------------------
                         required time                         15.510    
                         arrival time                          -6.476    
  -------------------------------------------------------------------
                         slack                                  9.035    

Slack (MET) :             9.104ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.696ns  (logic 0.413ns (15.316%)  route 2.283ns (84.684%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        -0.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.941ns = ( 15.943 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.315ns (routing 0.578ns, distribution 0.737ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C5LUT_SLICEL_I3_O)
                                                      0.158     5.717 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[9]_i_3/O
                         net (fo=6, routed)           0.237     5.954    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[9]_i_3_n_0
    SLICE_X82Y356        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.051     6.005 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_6/O
                         net (fo=7, routed)           0.218     6.223    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_6_n_0
    SLICE_X83Y357        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.125     6.348 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[12]_i_1/O
                         net (fo=1, routed)           0.058     6.406    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[12]
    SLICE_X83Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.315    15.943    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X83Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[12]/C
                         clock pessimism             -0.382    15.561    
                         clock uncertainty           -0.076    15.485    
    SLICE_X83Y357        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025    15.510    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[12]
  -------------------------------------------------------------------
                         required time                         15.510    
                         arrival time                          -6.406    
  -------------------------------------------------------------------
                         slack                                  9.104    

Slack (MET) :             9.105ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.695ns  (logic 0.375ns (13.914%)  route 2.320ns (86.086%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.941ns = ( 15.943 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.315ns (routing 0.578ns, distribution 0.737ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     5.705 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.499     6.204    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X81Y358        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     6.354 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[11]_i_1/O
                         net (fo=1, routed)           0.051     6.405    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[11]
    SLICE_X81Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.315    15.943    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[11]/C
                         clock pessimism             -0.382    15.561    
                         clock uncertainty           -0.076    15.485    
    SLICE_X81Y358        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025    15.510    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[11]
  -------------------------------------------------------------------
                         required time                         15.510    
                         arrival time                          -6.405    
  -------------------------------------------------------------------
                         slack                                  9.105    

Slack (MET) :             9.158ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.647ns  (logic 0.313ns (11.825%)  route 2.334ns (88.175%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.147ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.945ns = ( 15.947 - 12.002 ) 
    Source Clock Delay      (SCD):    3.710ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.523ns (routing 0.635ns, distribution 0.888ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.578ns, distribution 0.741ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.523     3.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X88Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y365        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.789 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[4]/Q
                         net (fo=18, routed)          1.770     5.559    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[8]
    SLICE_X84Y358        LUT5 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.146     5.705 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.492     6.197    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X82Y357        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.285 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[8]_i_1/O
                         net (fo=1, routed)           0.072     6.357    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[8]
    SLICE_X82Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.319    15.947    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[8]/C
                         clock pessimism             -0.382    15.565    
                         clock uncertainty           -0.076    15.489    
    SLICE_X82Y357        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025    15.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[8]
  -------------------------------------------------------------------
                         required time                         15.514    
                         arrival time                          -6.357    
  -------------------------------------------------------------------
                         slack                                  9.158    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.251ns  (logic 0.058ns (23.108%)  route 0.193ns (76.893%))
  Logic Levels:           0  
  Clock Path Skew:        0.163ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.720ns
    Source Clock Delay      (SCD):    3.939ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Net Delay (Source):      1.313ns (routing 0.578ns, distribution 0.735ns)
  Clock Net Delay (Destination): 1.533ns (routing 0.635ns, distribution 0.898ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.313     3.939    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y354        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     3.997 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_do_r_reg[10]/Q
                         net (fo=1, routed)           0.193     4.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/rd_din_mux[10]
    SLICE_X82Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.533     3.720    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/clk
    SLICE_X82Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[10]/C
                         clock pessimism              0.382     4.102    
    SLICE_X82Y360        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     4.164    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_MSTR2SL_PORT_IFACE/MA_RD_DIN_O_reg[10]
  -------------------------------------------------------------------
                         required time                         -4.164    
                         arrival time                           4.190    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[85]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[85]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.080ns  (logic 0.039ns (48.694%)  route 0.041ns (51.307%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.209ns
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    -0.158ns
  Clock Net Delay (Source):      0.820ns (routing 0.349ns, distribution 0.471ns)
  Clock Net Delay (Destination): 0.933ns (routing 0.390ns, distribution 0.543ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.820     2.361    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[85]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y351        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.400 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[85]/Q
                         net (fo=2, routed)           0.041     2.441    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[85]
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[85]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.933     2.209    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[85]/C
                         clock pessimism              0.158     2.367    
    SLICE_X81Y351        FDRE (Hold_HFF_SLICEL_C_D)
                                                      0.046     2.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[85]
  -------------------------------------------------------------------
                         required time                         -2.413    
                         arrival time                           2.441    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[97]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[97]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.081ns  (logic 0.039ns (48.148%)  route 0.042ns (51.852%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.211ns
    Source Clock Delay      (SCD):    2.363ns
    Clock Pessimism Removal (CPR):    -0.158ns
  Clock Net Delay (Source):      0.822ns (routing 0.349ns, distribution 0.473ns)
  Clock Net Delay (Destination): 0.935ns (routing 0.390ns, distribution 0.545ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.822     2.363    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[97]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y358        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.402 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[97]/Q
                         net (fo=2, routed)           0.042     2.444    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[97]
    SLICE_X82Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[97]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.935     2.211    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[97]/C
                         clock pessimism              0.158     2.369    
    SLICE_X82Y358        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.415    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[97]
  -------------------------------------------------------------------
                         required time                         -2.415    
                         arrival time                           2.444    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.192ns  (logic 0.060ns (31.250%)  route 0.132ns (68.750%))
  Logic Levels:           0  
  Clock Path Skew:        0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.705ns
    Source Clock Delay      (SCD):    3.985ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Net Delay (Source):      1.359ns (routing 0.578ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.518ns (routing 0.635ns, distribution 0.883ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.359     3.985    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X83Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y360        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.060     4.045 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[3]/Q
                         net (fo=2, routed)           0.132     4.177    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[24]
    SLICE_X83Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.518     3.705    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X83Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]/C
                         clock pessimism              0.382     4.087    
    SLICE_X83Y356        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.060     4.147    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -4.147    
                         arrival time                           4.177    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.082ns  (logic 0.039ns (47.561%)  route 0.043ns (52.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.214ns
    Source Clock Delay      (SCD):    2.366ns
    Clock Pessimism Removal (CPR):    -0.158ns
  Clock Net Delay (Source):      0.825ns (routing 0.349ns, distribution 0.476ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.390ns, distribution 0.548ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.825     2.366    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y359        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.405 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[18]/Q
                         net (fo=2, routed)           0.043     2.448    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[18]
    SLICE_X81Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[18]/C
                         clock pessimism              0.158     2.372    
    SLICE_X81Y359        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     2.418    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[18]
  -------------------------------------------------------------------
                         required time                         -2.418    
                         arrival time                           2.448    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.082ns  (logic 0.039ns (47.561%)  route 0.043ns (52.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.214ns
    Source Clock Delay      (SCD):    2.366ns
    Clock Pessimism Removal (CPR):    -0.158ns
  Clock Net Delay (Source):      0.825ns (routing 0.349ns, distribution 0.476ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.390ns, distribution 0.548ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.825     2.366    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y358        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.405 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[31]/Q
                         net (fo=2, routed)           0.043     2.448    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[31]
    SLICE_X81Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X81Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[31]/C
                         clock pessimism              0.158     2.372    
    SLICE_X81Y358        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     2.418    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[31]
  -------------------------------------------------------------------
                         required time                         -2.418    
                         arrival time                           2.448    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.082ns  (logic 0.039ns (47.561%)  route 0.043ns (52.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.219ns
    Source Clock Delay      (SCD):    2.371ns
    Clock Pessimism Removal (CPR):    -0.157ns
  Clock Net Delay (Source):      0.830ns (routing 0.349ns, distribution 0.481ns)
  Clock Net Delay (Destination): 0.944ns (routing 0.390ns, distribution 0.554ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.830     2.371    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y356        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.410 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[6]/Q
                         net (fo=1, routed)           0.043     2.453    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]_0[6]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.944     2.219    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
                         clock pessimism              0.157     2.377    
    SLICE_X84Y356        FDRE (Hold_EFF_SLICEL_C_D)
                                                      0.046     2.423    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.423    
                         arrival time                           2.453    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (47.074%)  route 0.044ns (52.926%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.214ns
    Source Clock Delay      (SCD):    2.366ns
    Clock Pessimism Removal (CPR):    -0.158ns
  Clock Net Delay (Source):      0.825ns (routing 0.349ns, distribution 0.476ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.390ns, distribution 0.548ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.825     2.366    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y350        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.405 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[5]/Q
                         net (fo=2, routed)           0.044     2.448    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[5]
    SLICE_X82Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[5]/C
                         clock pessimism              0.158     2.372    
    SLICE_X82Y350        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.418    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.418    
                         arrival time                           2.448    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[89]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[89]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.935%)  route 0.044ns (53.065%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.215ns
    Source Clock Delay      (SCD):    2.367ns
    Clock Pessimism Removal (CPR):    -0.158ns
  Clock Net Delay (Source):      0.826ns (routing 0.349ns, distribution 0.477ns)
  Clock Net Delay (Destination): 0.939ns (routing 0.390ns, distribution 0.549ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.826     2.367    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[89]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y357        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.406 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[89]/Q
                         net (fo=2, routed)           0.044     2.450    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[89]
    SLICE_X82Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[89]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.939     2.215    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X82Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[89]/C
                         clock pessimism              0.158     2.373    
    SLICE_X82Y357        FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     2.419    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[89]
  -------------------------------------------------------------------
                         required time                         -2.419    
                         arrival time                           2.450    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.084ns  (logic 0.039ns (46.513%)  route 0.045ns (53.487%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.207ns
    Source Clock Delay      (SCD):    2.360ns
    Clock Pessimism Removal (CPR):    -0.159ns
  Clock Net Delay (Source):      0.819ns (routing 0.349ns, distribution 0.470ns)
  Clock Net Delay (Destination): 0.931ns (routing 0.390ns, distribution 0.541ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.819     2.360    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y359        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.399 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/Q
                         net (fo=2, routed)           0.045     2.443    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[23]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.931     2.207    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]/C
                         clock pessimism              0.159     2.366    
    SLICE_X85Y359        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     2.412    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[23]
  -------------------------------------------------------------------
                         required time                         -2.412    
                         arrival time                           2.443    
  -------------------------------------------------------------------
                         slack                                  0.032    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout5
Waveform(ns):       { 0.000 6.001 }
Period(ns):         12.002
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I            n/a            1.290         12.002      10.712     BUFGCE_X0Y118  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/I
Min Period        n/a     MMCME4_ADV/CLKOUT5  n/a            1.071         12.002      10.931     MMCM_X0Y4      d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X86Y360  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        0.969ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.028ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.985ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.969ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.936ns  (logic 0.530ns (10.738%)  route 4.406ns (89.262%))
  Logic Levels:           5  (LUT6=4 MUXF7=1)
  Clock Path Skew:        -0.053ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.389ns = ( 10.390 - 6.001 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.932ns (routing 0.709ns, distribution 1.223ns)
  Clock Net Delay (Destination): 1.742ns (routing 0.644ns, distribution 1.098ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.932     4.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.224 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          0.252     4.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[21]
    SLICE_X88Y337        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     4.625 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23/O
                         net (fo=9, routed)           0.431     5.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23_n_0
    SLICE_X87Y350        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     5.204 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5/O
                         net (fo=66, routed)          2.280     7.483    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5_n_0
    SLICE_X81Y202        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     7.518 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[1]_i_4/O
                         net (fo=1, routed)           1.397     8.915    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[1]_i_4_n_0
    SLICE_X82Y315        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.053     8.968 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[1]_i_2/O
                         net (fo=1, routed)           0.014     8.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[1]_i_2_n_0
    SLICE_X82Y315        MUXF7 (Prop_F7MUX_GH_SLICEM_I0_O)
                                                      0.066     9.048 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[1]_i_1/O
                         net (fo=1, routed)           0.032     9.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[1]_i_1_n_0
    SLICE_X82Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.742    10.390    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[1]/C
                         clock pessimism             -0.298    10.093    
                         clock uncertainty           -0.068    10.024    
    SLICE_X82Y315        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025    10.049    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[1]
  -------------------------------------------------------------------
                         required time                         10.049    
                         arrival time                          -9.080    
  -------------------------------------------------------------------
                         slack                                  0.969    

Slack (MET) :             1.181ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.720ns  (logic 0.731ns (15.487%)  route 3.989ns (84.513%))
  Logic Levels:           5  (LUT6=4 MUXF7=1)
  Clock Path Skew:        -0.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.386ns = ( 10.387 - 6.001 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.932ns (routing 0.709ns, distribution 1.223ns)
  Clock Net Delay (Destination): 1.739ns (routing 0.644ns, distribution 1.095ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.932     4.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.224 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          0.252     4.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[21]
    SLICE_X88Y337        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     4.625 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23/O
                         net (fo=9, routed)           0.431     5.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23_n_0
    SLICE_X87Y350        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     5.204 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5/O
                         net (fo=66, routed)          2.308     7.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5_n_0
    SLICE_X81Y203        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.146     7.658 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[10]_i_4/O
                         net (fo=1, routed)           0.958     8.616    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[10]_i_4_n_0
    SLICE_X81Y316        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     8.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[10]_i_2/O
                         net (fo=1, routed)           0.009     8.771    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[10]_i_2_n_0
    SLICE_X81Y316        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     8.834 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[10]_i_1/O
                         net (fo=1, routed)           0.031     8.865    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[10]_i_1_n_0
    SLICE_X81Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.739    10.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[10]/C
                         clock pessimism             -0.298    10.090    
                         clock uncertainty           -0.068    10.021    
    SLICE_X81Y316        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.046    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[10]
  -------------------------------------------------------------------
                         required time                         10.046    
                         arrival time                          -8.865    
  -------------------------------------------------------------------
                         slack                                  1.181    

Slack (MET) :             1.184ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.722ns  (logic 0.686ns (14.527%)  route 4.036ns (85.473%))
  Logic Levels:           5  (LUT6=4 MUXF7=1)
  Clock Path Skew:        -0.051ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.391ns = ( 10.392 - 6.001 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.932ns (routing 0.709ns, distribution 1.223ns)
  Clock Net Delay (Destination): 1.744ns (routing 0.644ns, distribution 1.100ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.932     4.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.224 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          0.252     4.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[21]
    SLICE_X88Y337        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     4.625 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23/O
                         net (fo=9, routed)           0.431     5.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23_n_0
    SLICE_X87Y350        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     5.204 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5/O
                         net (fo=66, routed)          2.349     7.552    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5_n_0
    SLICE_X81Y202        LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.096     7.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[7]_i_4/O
                         net (fo=1, routed)           0.964     8.612    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[7]_i_4_n_0
    SLICE_X81Y312        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     8.762 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[7]_i_2/O
                         net (fo=1, routed)           0.010     8.772    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[7]_i_2_n_0
    SLICE_X81Y312        MUXF7 (Prop_F7MUX_GH_SLICEL_I0_O)
                                                      0.064     8.836 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[7]_i_1/O
                         net (fo=1, routed)           0.031     8.867    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[7]_i_1_n_0
    SLICE_X81Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.744    10.392    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[7]/C
                         clock pessimism             -0.298    10.095    
                         clock uncertainty           -0.068    10.026    
    SLICE_X81Y312        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025    10.051    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[7]
  -------------------------------------------------------------------
                         required time                         10.051    
                         arrival time                          -8.867    
  -------------------------------------------------------------------
                         slack                                  1.184    

Slack (MET) :             1.188ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.719ns  (logic 0.630ns (13.349%)  route 4.089ns (86.651%))
  Logic Levels:           5  (LUT6=4 MUXF7=1)
  Clock Path Skew:        -0.050ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.392ns = ( 10.393 - 6.001 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.932ns (routing 0.709ns, distribution 1.223ns)
  Clock Net Delay (Destination): 1.745ns (routing 0.644ns, distribution 1.101ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.932     4.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.224 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          0.252     4.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[21]
    SLICE_X88Y337        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     4.625 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23/O
                         net (fo=9, routed)           0.431     5.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23_n_0
    SLICE_X87Y350        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     5.204 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5/O
                         net (fo=66, routed)          2.300     7.503    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5_n_0
    SLICE_X81Y203        LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.098     7.601 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_4/O
                         net (fo=1, routed)           1.061     8.662    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_4_n_0
    SLICE_X82Y310        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     8.752 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_2/O
                         net (fo=1, routed)           0.014     8.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[2]_i_2_n_0
    SLICE_X82Y310        MUXF7 (Prop_F7MUX_GH_SLICEM_I0_O)
                                                      0.066     8.832 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]_i_1/O
                         net (fo=1, routed)           0.032     8.864    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]_i_1_n_0
    SLICE_X82Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.745    10.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]/C
                         clock pessimism             -0.298    10.096    
                         clock uncertainty           -0.068    10.027    
    SLICE_X82Y310        FDRE (Setup_HFF_SLICEM_C_D)
                                                      0.025    10.052    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[2]
  -------------------------------------------------------------------
                         required time                         10.052    
                         arrival time                          -8.864    
  -------------------------------------------------------------------
                         slack                                  1.188    

Slack (MET) :             1.222ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.678ns  (logic 0.599ns (12.805%)  route 4.079ns (87.195%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.394ns = ( 10.395 - 6.001 ) 
    Source Clock Delay      (SCD):    4.154ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.941ns (routing 0.709ns, distribution 1.232ns)
  Clock Net Delay (Destination): 1.747ns (routing 0.644ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.941     4.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y337        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.233 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/Q
                         net (fo=39, routed)          0.704     4.937    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[9]
    SLICE_X86Y357        LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.066     5.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.205     5.208    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X86Y351        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     5.245 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.054     5.299    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X86Y351        LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.100     5.399 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          2.120     7.519    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X82Y201        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.101     7.620 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[6]_i_4/O
                         net (fo=1, routed)           0.948     8.568    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[6]_i_4_n_0
    SLICE_X82Y306        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     8.717 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[6]_i_2/O
                         net (fo=1, routed)           0.017     8.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[6]_i_2_n_0
    SLICE_X82Y306        MUXF7 (Prop_F7MUX_AB_SLICEM_I0_O)
                                                      0.067     8.801 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]_i_1/O
                         net (fo=1, routed)           0.031     8.832    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]_i_1_n_0
    SLICE_X82Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.747    10.395    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]/C
                         clock pessimism             -0.298    10.098    
                         clock uncertainty           -0.068    10.029    
    SLICE_X82Y306        FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025    10.054    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[6]
  -------------------------------------------------------------------
                         required time                         10.054    
                         arrival time                          -8.832    
  -------------------------------------------------------------------
                         slack                                  1.222    

Slack (MET) :             1.223ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.682ns  (logic 0.525ns (11.213%)  route 4.157ns (88.787%))
  Logic Levels:           5  (LUT6=4 MUXF7=1)
  Clock Path Skew:        -0.053ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.390ns = ( 10.391 - 6.001 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.932ns (routing 0.709ns, distribution 1.223ns)
  Clock Net Delay (Destination): 1.743ns (routing 0.644ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.932     4.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.224 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          0.252     4.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[21]
    SLICE_X88Y337        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     4.625 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23/O
                         net (fo=9, routed)           0.431     5.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23_n_0
    SLICE_X87Y350        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     5.204 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5/O
                         net (fo=66, routed)          2.288     7.491    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5_n_0
    SLICE_X81Y202        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     7.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[13]_i_4/O
                         net (fo=1, routed)           1.148     8.674    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[13]_i_4_n_0
    SLICE_X84Y311        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.051     8.725 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[13]_i_2/O
                         net (fo=1, routed)           0.009     8.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[13]_i_2_n_0
    SLICE_X84Y311        MUXF7 (Prop_F7MUX_AB_SLICEL_I0_O)
                                                      0.063     8.797 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]_i_1/O
                         net (fo=1, routed)           0.030     8.827    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]_i_1_n_0
    SLICE_X84Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.743    10.391    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y311        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]/C
                         clock pessimism             -0.298    10.093    
                         clock uncertainty           -0.068    10.025    
    SLICE_X84Y311        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025    10.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[13]
  -------------------------------------------------------------------
                         required time                         10.050    
                         arrival time                          -8.827    
  -------------------------------------------------------------------
                         slack                                  1.223    

Slack (MET) :             1.246ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.646ns  (logic 0.558ns (12.010%)  route 4.088ns (87.990%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.065ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.386ns = ( 10.387 - 6.001 ) 
    Source Clock Delay      (SCD):    4.154ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.941ns (routing 0.709ns, distribution 1.232ns)
  Clock Net Delay (Destination): 1.739ns (routing 0.644ns, distribution 1.095ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.941     4.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y337        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.233 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/Q
                         net (fo=39, routed)          0.704     4.937    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[9]
    SLICE_X86Y357        LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.066     5.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.205     5.208    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X86Y351        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     5.245 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.054     5.299    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X86Y351        LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.100     5.399 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          2.031     7.430    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X81Y201        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.123     7.553 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[9]_i_4/O
                         net (fo=1, routed)           1.055     8.608    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[9]_i_4_n_0
    SLICE_X81Y316        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.090     8.698 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[9]_i_2/O
                         net (fo=1, routed)           0.009     8.707    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[9]_i_2_n_0
    SLICE_X81Y316        MUXF7 (Prop_F7MUX_AB_SLICEL_I0_O)
                                                      0.063     8.770 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[9]_i_1/O
                         net (fo=1, routed)           0.030     8.800    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[9]_i_1_n_0
    SLICE_X81Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.739    10.387    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[9]/C
                         clock pessimism             -0.298    10.090    
                         clock uncertainty           -0.068    10.021    
    SLICE_X81Y316        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025    10.046    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[9]
  -------------------------------------------------------------------
                         required time                         10.046    
                         arrival time                          -8.800    
  -------------------------------------------------------------------
                         slack                                  1.246    

Slack (MET) :             1.249ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.656ns  (logic 0.599ns (12.865%)  route 4.057ns (87.135%))
  Logic Levels:           5  (LUT6=4 MUXF7=1)
  Clock Path Skew:        -0.053ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.390ns = ( 10.391 - 6.001 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.932ns (routing 0.709ns, distribution 1.223ns)
  Clock Net Delay (Destination): 1.743ns (routing 0.644ns, distribution 1.099ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.932     4.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.224 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          0.252     4.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[21]
    SLICE_X88Y337        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     4.625 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23/O
                         net (fo=9, routed)           0.431     5.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23_n_0
    SLICE_X87Y350        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     5.204 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5/O
                         net (fo=66, routed)          2.299     7.503    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5_n_0
    SLICE_X81Y201        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.124     7.627 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[3]_i_4/O
                         net (fo=1, routed)           1.036     8.663    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[3]_i_4_n_0
    SLICE_X81Y317        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     8.699 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[3]_i_2/O
                         net (fo=1, routed)           0.009     8.708    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[3]_i_2_n_0
    SLICE_X81Y317        MUXF7 (Prop_F7MUX_AB_SLICEL_I0_O)
                                                      0.063     8.771 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]_i_1/O
                         net (fo=1, routed)           0.030     8.801    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]_i_1_n_0
    SLICE_X81Y317        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.743    10.391    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y317        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]/C
                         clock pessimism             -0.298    10.093    
                         clock uncertainty           -0.068    10.025    
    SLICE_X81Y317        FDRE (Setup_BFF_SLICEL_C_D)
                                                      0.025    10.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[3]
  -------------------------------------------------------------------
                         required time                         10.050    
                         arrival time                          -8.801    
  -------------------------------------------------------------------
                         slack                                  1.249    

Slack (MET) :             1.286ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.623ns  (logic 0.595ns (12.870%)  route 4.028ns (87.130%))
  Logic Levels:           5  (LUT6=4 MUXF7=1)
  Clock Path Skew:        -0.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.394ns = ( 10.395 - 6.001 ) 
    Source Clock Delay      (SCD):    4.145ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.932ns (routing 0.709ns, distribution 1.223ns)
  Clock Net Delay (Destination): 1.747ns (routing 0.644ns, distribution 1.103ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.932     4.145    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.224 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          0.252     4.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[21]
    SLICE_X88Y337        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     4.625 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23/O
                         net (fo=9, routed)           0.431     5.056    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_23_n_0
    SLICE_X87Y350        LUT6 (Prop_F6LUT_SLICEM_I5_O)
                                                      0.148     5.204 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5/O
                         net (fo=66, routed)          2.353     7.556    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_5_n_0
    SLICE_X81Y202        LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     7.655 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[5]_i_4/O
                         net (fo=1, routed)           0.936     8.591    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[5]_i_4_n_0
    SLICE_X82Y306        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.051     8.642 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[5]_i_2/O
                         net (fo=1, routed)           0.025     8.667    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[5]_i_2_n_0
    SLICE_X82Y306        MUXF7 (Prop_F7MUX_CD_SLICEM_I0_O)
                                                      0.069     8.736 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]_i_1/O
                         net (fo=1, routed)           0.032     8.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]_i_1_n_0
    SLICE_X82Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.747    10.395    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y306        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]/C
                         clock pessimism             -0.298    10.098    
                         clock uncertainty           -0.068    10.029    
    SLICE_X82Y306        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025    10.054    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[5]
  -------------------------------------------------------------------
                         required time                         10.054    
                         arrival time                          -8.768    
  -------------------------------------------------------------------
                         slack                                  1.286    

Slack (MET) :             1.307ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.591ns  (logic 0.523ns (11.393%)  route 4.068ns (88.607%))
  Logic Levels:           6  (LUT2=1 LUT5=1 LUT6=3 MUXF7=1)
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.392ns = ( 10.393 - 6.001 ) 
    Source Clock Delay      (SCD):    4.154ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.941ns (routing 0.709ns, distribution 1.232ns)
  Clock Net Delay (Destination): 1.745ns (routing 0.644ns, distribution 1.101ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.941     4.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y337        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y337        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     4.233 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[9]/Q
                         net (fo=39, routed)          0.704     4.937    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_address_riuclk[9]
    SLICE_X86Y357        LUT2 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.066     5.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26/O
                         net (fo=7, routed)           0.205     5.208    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[7]_INST_0_i_26_n_0
    SLICE_X86Y351        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     5.245 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11/O
                         net (fo=2, routed)           0.054     5.299    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_nibble_8[1]_INST_0_i_11_n_0
    SLICE_X86Y351        LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.100     5.399 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9/O
                         net (fo=64, routed)          2.026     7.425    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[15]_i_9_n_0
    SLICE_X81Y204        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.089     7.514 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[14]_i_4/O
                         net (fo=1, routed)           1.038     8.552    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[14]_i_4_n_0
    SLICE_X81Y315        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     8.641 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[14]_i_2/O
                         net (fo=1, routed)           0.009     8.650    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data[14]_i_2_n_0
    SLICE_X81Y315        MUXF7 (Prop_F7MUX_CD_SLICEL_I0_O)
                                                      0.063     8.713 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[14]_i_1/O
                         net (fo=1, routed)           0.031     8.744    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[14]_i_1_n_0
    SLICE_X81Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.745    10.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[14]/C
                         clock pessimism             -0.298    10.095    
                         clock uncertainty           -0.068    10.027    
    SLICE_X81Y315        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    10.052    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu2clb_vld_read_data_reg[14]
  -------------------------------------------------------------------
                         required time                         10.052    
                         arrival time                          -8.744    
  -------------------------------------------------------------------
                         slack                                  1.307    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.028ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/fab_riu_rst_pipe_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/fab_riu_rst_pipe_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.081ns  (logic 0.039ns (48.148%)  route 0.042ns (51.852%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.518ns
    Source Clock Delay      (SCD):    2.639ns
    Clock Pessimism Removal (CPR):    -0.127ns
  Clock Net Delay (Source):      1.082ns (routing 0.391ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.224ns (routing 0.439ns, distribution 0.785ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.082     2.639    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X96Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/fab_riu_rst_pipe_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y350        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     2.678 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/fab_riu_rst_pipe_reg[9]/Q
                         net (fo=2, routed)           0.042     2.720    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/fab_riu_rst_pipe[9]
    SLICE_X96Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/fab_riu_rst_pipe_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.224     2.518    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X96Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/fab_riu_rst_pipe_reg[10]/C
                         clock pessimism              0.127     2.645    
    SLICE_X96Y350        FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.047     2.692    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/fab_riu_rst_pipe_reg[10]
  -------------------------------------------------------------------
                         required time                         -2.692    
                         arrival time                           2.720    
  -------------------------------------------------------------------
                         slack                                  0.028    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.082ns  (logic 0.038ns (46.521%)  route 0.044ns (53.479%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.516ns
    Source Clock Delay      (SCD):    2.636ns
    Clock Pessimism Removal (CPR):    -0.126ns
  Clock Net Delay (Source):      1.079ns (routing 0.391ns, distribution 0.688ns)
  Clock Net Delay (Destination): 1.222ns (routing 0.439ns, distribution 0.783ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.079     2.636    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X82Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y345        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.674 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[6]/Q
                         net (fo=2, routed)           0.044     2.718    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/io_write_data_riuclk[6]
    SLICE_X82Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.222     2.516    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y345        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[6]/C
                         clock pessimism              0.126     2.642    
    SLICE_X82Y345        FDRE (Hold_CFF2_SLICEM_C_D)
                                                      0.047     2.689    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[6]
  -------------------------------------------------------------------
                         required time                         -2.689    
                         arrival time                           2.718    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.096ns  (logic 0.039ns (40.625%)  route 0.057ns (59.375%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.502ns
    Source Clock Delay      (SCD):    2.622ns
    Clock Pessimism Removal (CPR):    -0.139ns
  Clock Net Delay (Source):      1.065ns (routing 0.391ns, distribution 0.674ns)
  Clock Net Delay (Destination): 1.208ns (routing 0.439ns, distribution 0.769ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.065     2.622    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y332        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.661 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[11]/Q
                         net (fo=1, routed)           0.057     2.718    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/IO_Read_Data[11]
    SLICE_X88Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.208     2.502    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X88Y331        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[11]/C
                         clock pessimism              0.139     2.641    
    SLICE_X88Y331        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.047     2.688    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[11]
  -------------------------------------------------------------------
                         required time                         -2.688    
                         arrival time                           2.718    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_div_instr_I_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.132ns  (logic 0.058ns (43.835%)  route 0.074ns (56.165%))
  Logic Levels:           0  
  Clock Path Skew:        0.039ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.181ns
    Source Clock Delay      (SCD):    4.392ns
    Clock Pessimism Removal (CPR):    -0.250ns
  Clock Net Delay (Source):      1.745ns (routing 0.644ns, distribution 1.101ns)
  Clock Net Delay (Destination): 1.968ns (routing 0.709ns, distribution 1.259ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.745     4.392    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X91Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_div_instr_I_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y357        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     4.450 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_is_div_instr_I_reg/Q
                         net (fo=4, routed)           0.074     4.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Is_Div_Instr
    SLICE_X91Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.968     4.181    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X91Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg/C
                         clock pessimism              0.250     4.431    
    SLICE_X91Y356        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     4.493    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_is_div_instr_I_reg
  -------------------------------------------------------------------
                         required time                         -4.493    
                         arrival time                           4.524    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[4].Gen_Instr_DFF/Using_FPGA.Native/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Op_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.058ns (42.755%)  route 0.078ns (57.246%))
  Logic Levels:           0  
  Clock Path Skew:        0.038ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.183ns
    Source Clock Delay      (SCD):    4.384ns
    Clock Pessimism Removal (CPR):    -0.239ns
  Clock Net Delay (Source):      1.737ns (routing 0.644ns, distribution 1.093ns)
  Clock Net Delay (Destination): 1.970ns (routing 0.709ns, distribution 1.261ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.737     4.384    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[4].Gen_Instr_DFF/Clk
    SLICE_X91Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[4].Gen_Instr_DFF/Using_FPGA.Native/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y322        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.442 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[4].Gen_Instr_DFF/Using_FPGA.Native/Q
                         net (fo=29, routed)          0.078     4.520    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/of_instr_raw[4]
    SLICE_X90Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Op_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.970     4.183    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X90Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Op_reg[0]/C
                         clock pessimism              0.239     4.422    
    SLICE_X90Y322        FDRE (Hold_HFF2_SLICEM_C_D)
                                                      0.062     4.484    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/EX_Logic_Op_reg[0]
  -------------------------------------------------------------------
                         required time                         -4.484    
                         arrival time                           4.520    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.058ns (34.320%)  route 0.111ns (65.681%))
  Logic Levels:           0  
  Clock Path Skew:        0.071ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.152ns
    Source Clock Delay      (SCD):    4.378ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Net Delay (Source):      1.731ns (routing 0.644ns, distribution 1.087ns)
  Clock Net Delay (Destination): 1.939ns (routing 0.709ns, distribution 1.230ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.731     4.378    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X89Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y341        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     4.436 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[5]/Q
                         net (fo=1, routed)           0.111     4.547    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_ub[5]
    SLICE_X88Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.939     4.152    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]/C
                         clock pessimism              0.298     4.449    
    SLICE_X88Y341        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     4.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[3]
  -------------------------------------------------------------------
                         required time                         -4.511    
                         arrival time                           4.547    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[7]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][7]_srl4/D
                            (rising edge-triggered cell SRL16E clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.182ns  (logic 0.059ns (32.452%)  route 0.123ns (67.548%))
  Logic Levels:           0  
  Clock Path Skew:        0.114ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.187ns
    Source Clock Delay      (SCD):    4.371ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Net Delay (Source):      1.724ns (routing 0.644ns, distribution 1.080ns)
  Clock Net Delay (Destination): 1.974ns (routing 0.709ns, distribution 1.265ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.724     4.371    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X88Y341        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y341        FDSE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[7]/Q
                         net (fo=4, routed)           0.123     4.552    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/S117_in
    SLICE_X90Y341        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][7]_srl4/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.974     4.187    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X90Y341        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][7]_srl4/CLK
                         clock pessimism              0.298     4.484    
    SLICE_X90Y341        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     4.516    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][7]_srl4
  -------------------------------------------------------------------
                         required time                         -4.516    
                         arrival time                           4.552    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[29]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][29]_srl4/D
                            (rising edge-triggered cell SRL16E clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.210ns  (logic 0.058ns (27.668%)  route 0.152ns (72.332%))
  Logic Levels:           0  
  Clock Path Skew:        0.116ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.179ns
    Source Clock Delay      (SCD):    4.360ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Net Delay (Source):      1.713ns (routing 0.644ns, distribution 1.069ns)
  Clock Net Delay (Destination): 1.966ns (routing 0.709ns, distribution 1.257ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.713     4.360    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X88Y336        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[29]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y336        FDSE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.418 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/if_pc_reg[29]/Q
                         net (fo=4, routed)           0.152     4.570    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/S
    SLICE_X90Y335        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][29]_srl4/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.966     4.179    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/Clk
    SLICE_X90Y335        SRL16E                                       r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][29]_srl4/CLK
                         clock pessimism              0.298     4.476    
    SLICE_X90Y335        SRL16E (Hold_F5LUT_SLICEM_CLK_D)
                                                      0.056     4.532    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PC_Module_I/PC_Buffer_reg[3][29]_srl4
  -------------------------------------------------------------------
                         required time                         -4.532    
                         arrival time                           4.570    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.172ns  (logic 0.058ns (33.721%)  route 0.114ns (66.279%))
  Logic Levels:           0  
  Clock Path Skew:        0.074ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.152ns
    Source Clock Delay      (SCD):    4.376ns
    Clock Pessimism Removal (CPR):    -0.298ns
  Clock Net Delay (Source):      1.729ns (routing 0.644ns, distribution 1.085ns)
  Clock Net Delay (Destination): 1.939ns (routing 0.709ns, distribution 1.230ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.729     4.376    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X89Y342        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y342        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     4.434 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[7]/Q
                         net (fo=1, routed)           0.114     4.548    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_ub[7]
    SLICE_X88Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.939     4.152    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/C
                         clock pessimism              0.298     4.449    
    SLICE_X88Y341        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.060     4.509    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]
  -------------------------------------------------------------------
                         required time                         -4.509    
                         arrival time                           4.548    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.039ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.125ns  (logic 0.038ns (30.400%)  route 0.087ns (69.600%))
  Logic Levels:           0  
  Clock Path Skew:        0.039ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.504ns
    Source Clock Delay      (SCD):    2.633ns
    Clock Pessimism Removal (CPR):    -0.168ns
  Clock Net Delay (Source):      1.076ns (routing 0.391ns, distribution 0.685ns)
  Clock Net Delay (Destination): 1.210ns (routing 0.439ns, distribution 0.771ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.076     2.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X89Y344        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y344        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.671 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Address_reg[24]/Q
                         net (fo=1, routed)           0.087     2.758    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_ub[24]
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.210     2.504    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y346        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
                         clock pessimism              0.168     2.672    
    SLICE_X88Y346        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     2.719    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]
  -------------------------------------------------------------------
                         required time                         -2.719    
                         arrival time                           2.758    
  -------------------------------------------------------------------
                         slack                                  0.039    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout6
Waveform(ns):       { 0.000 3.001 }
Period(ns):         6.001
Sources:            { d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6 }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y47  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y28  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y44  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y45  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y46  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.833       0.985      BITSLICE_CONTROL_X0Y24  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.833       0.985      BITSLICE_CONTROL_X0Y25  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.831       0.987      BITSLICE_CONTROL_X0Y32  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.831       0.987      BITSLICE_CONTROL_X0Y33  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.830       0.988      BITSLICE_CONTROL_X0Y26  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.830       0.988      BITSLICE_CONTROL_X0Y31  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.828       0.990      BITSLICE_CONTROL_X0Y27  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.828       0.990      BITSLICE_CONTROL_X0Y29  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.828       0.990      BITSLICE_CONTROL_X0Y34  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.828       0.990      BITSLICE_CONTROL_X0Y39  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       11.556ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.556ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.471ns  (logic 0.081ns (17.197%)  route 0.390ns (82.803%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X88Y362        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.390     0.471    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X87Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X87Y362        FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.471    
  -------------------------------------------------------------------
                         slack                                 11.556    

Slack (MET) :             11.613ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.414ns  (logic 0.079ns (19.082%)  route 0.335ns (80.918%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X88Y362        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.335     0.414    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X87Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X87Y362        FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.414    
  -------------------------------------------------------------------
                         slack                                 11.613    

Slack (MET) :             11.614ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.413ns  (logic 0.076ns (18.402%)  route 0.337ns (81.598%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y366                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X82Y366        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.337     0.413    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X83Y367        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X83Y367        FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.413    
  -------------------------------------------------------------------
                         slack                                 11.614    

Slack (MET) :             11.677ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.350ns  (logic 0.079ns (22.571%)  route 0.271ns (77.429%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y367                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X82Y367        FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.271     0.350    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X82Y367        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X82Y367        FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.350    
  -------------------------------------------------------------------
                         slack                                 11.677    

Slack (MET) :             11.679ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.348ns  (logic 0.079ns (22.701%)  route 0.269ns (77.299%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X88Y362        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.269     0.348    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X88Y362        FDCE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.348    
  -------------------------------------------------------------------
                         slack                                 11.679    

Slack (MET) :             11.716ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.311ns  (logic 0.076ns (24.437%)  route 0.235ns (75.563%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y367                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X82Y367        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.235     0.311    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X82Y367        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X82Y367        FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.311    
  -------------------------------------------------------------------
                         slack                                 11.716    

Slack (MET) :             11.720ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.307ns  (logic 0.080ns (26.059%)  route 0.227ns (73.941%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y366                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X82Y366        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.227     0.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X83Y367        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X83Y367        FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.307    
  -------------------------------------------------------------------
                         slack                                 11.720    

Slack (MET) :             11.794ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.233ns  (logic 0.079ns (33.906%)  route 0.154ns (66.094%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X88Y362        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.154     0.233    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X88Y362        FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.233    
  -------------------------------------------------------------------
                         slack                                 11.794    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        2.147ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.147ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.878ns  (logic 0.077ns (8.770%)  route 0.801ns (91.230%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
    SLICE_X87Y358        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     0.077 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/Q
                         net (fo=1, routed)           0.801     0.878    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[13]
    SLICE_X88Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X88Y356        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.878    
  -------------------------------------------------------------------
                         slack                                  2.147    

Slack (MET) :             2.490ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.535ns  (logic 0.079ns (14.766%)  route 0.456ns (85.234%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y354                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
    SLICE_X86Y354        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/Q
                         net (fo=1, routed)           0.456     0.535    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[2]
    SLICE_X86Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y354        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.535    
  -------------------------------------------------------------------
                         slack                                  2.490    

Slack (MET) :             2.491ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.534ns  (logic 0.078ns (14.607%)  route 0.456ns (85.393%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/C
    SLICE_X87Y358        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[14]/Q
                         net (fo=1, routed)           0.456     0.534    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[14]
    SLICE_X89Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X89Y355        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.534    
  -------------------------------------------------------------------
                         slack                                  2.491    

Slack (MET) :             2.513ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.512ns  (logic 0.076ns (14.844%)  route 0.436ns (85.156%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y359                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/C
    SLICE_X86Y359        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[8]/Q
                         net (fo=1, routed)           0.436     0.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[8]
    SLICE_X86Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y358        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.512    
  -------------------------------------------------------------------
                         slack                                  2.513    

Slack (MET) :             2.556ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.469ns  (logic 0.078ns (16.631%)  route 0.391ns (83.369%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/C
    SLICE_X87Y358        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[12]/Q
                         net (fo=1, routed)           0.391     0.469    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[12]
    SLICE_X88Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X88Y356        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[12].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.469    
  -------------------------------------------------------------------
                         slack                                  2.556    

Slack (MET) :             2.574ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.451ns  (logic 0.080ns (17.738%)  route 0.371ns (82.262%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y354                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
    SLICE_X89Y354        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/Q
                         net (fo=1, routed)           0.371     0.451    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[1]
    SLICE_X86Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y354        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.451    
  -------------------------------------------------------------------
                         slack                                  2.574    

Slack (MET) :             2.583ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.442ns  (logic 0.079ns (17.873%)  route 0.363ns (82.127%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y356                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
    SLICE_X84Y356        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/Q
                         net (fo=1, routed)           0.363     0.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[5]
    SLICE_X86Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y355        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.442    
  -------------------------------------------------------------------
                         slack                                  2.583    

Slack (MET) :             2.585ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.440ns  (logic 0.079ns (17.955%)  route 0.361ns (82.045%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y359                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/C
    SLICE_X83Y359        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[7]/Q
                         net (fo=1, routed)           0.361     0.440    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[7]
    SLICE_X86Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y359        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.440    
  -------------------------------------------------------------------
                         slack                                  2.585    

Slack (MET) :             2.608ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.417ns  (logic 0.079ns (18.945%)  route 0.338ns (81.055%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y359                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
    SLICE_X82Y359        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/Q
                         net (fo=1, routed)           0.338     0.417    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[0]
    SLICE_X83Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X83Y352        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.417    
  -------------------------------------------------------------------
                         slack                                  2.608    

Slack (MET) :             2.613ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.412ns  (logic 0.078ns (18.932%)  route 0.334ns (81.068%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y356                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
    SLICE_X82Y356        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/Q
                         net (fo=1, routed)           0.334     0.412    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[8]
    SLICE_X83Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X83Y351        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.412    
  -------------------------------------------------------------------
                         slack                                  2.613    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        1.078ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.078ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[19].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.947ns  (logic 0.076ns (3.903%)  route 1.871ns (96.097%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y337                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[19]/C
    SLICE_X89Y337        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[19]/Q
                         net (fo=3, routed)           1.871     1.947    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[19]
    SLICE_X87Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[19].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X87Y310        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[19].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.947    
  -------------------------------------------------------------------
                         slack                                  1.078    

Slack (MET) :             1.161ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.864ns  (logic 0.078ns (4.185%)  route 1.786ns (95.815%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y339                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/C
    SLICE_X86Y339        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_strobe_riuclk_reg/Q
                         net (fo=16, routed)          1.786     1.864    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/D[0]
    SLICE_X84Y305        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X84Y305        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_strobe_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.864    
  -------------------------------------------------------------------
                         slack                                  1.161    

Slack (MET) :             1.249ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.776ns  (logic 0.079ns (4.447%)  route 1.697ns (95.553%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y348                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/C
    SLICE_X89Y348        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[23]/Q
                         net (fo=46, routed)          1.697     1.776    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X88Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X88Y307        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[23].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.776    
  -------------------------------------------------------------------
                         slack                                  1.249    

Slack (MET) :             1.460ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.565ns  (logic 0.079ns (5.047%)  route 1.486ns (94.953%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/C
    SLICE_X88Y346        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[21]/Q
                         net (fo=41, routed)          1.486     1.565    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[21]
    SLICE_X88Y304        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X88Y304        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[21].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.565    
  -------------------------------------------------------------------
                         slack                                  1.460    

Slack (MET) :             1.671ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.354ns  (logic 0.080ns (5.910%)  route 1.274ns (94.090%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
    SLICE_X88Y346        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/Q
                         net (fo=41, routed)          1.274     1.354    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[22]
    SLICE_X87Y300        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X87Y300        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.354    
  -------------------------------------------------------------------
                         slack                                  1.671    

Slack (MET) :             1.985ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.040ns  (logic 0.081ns (7.790%)  route 0.959ns (92.210%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y341                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/C
    SLICE_X88Y341        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/Q
                         net (fo=46, routed)          0.959     1.040    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[7]
    SLICE_X86Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y310        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.040    
  -------------------------------------------------------------------
                         slack                                  1.985    

Slack (MET) :             2.079ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.946ns  (logic 0.079ns (8.351%)  route 0.867ns (91.649%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y341                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/C
    SLICE_X88Y341        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[0]/Q
                         net (fo=34, routed)          0.867     0.946    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[0]
    SLICE_X85Y279        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X85Y279        FDRE (Setup_FFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.946    
  -------------------------------------------------------------------
                         slack                                  2.079    

Slack (MET) :             2.098ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.927ns  (logic 0.079ns (8.519%)  route 0.848ns (91.481%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y339                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[12]/C
    SLICE_X86Y339        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[12]/Q
                         net (fo=49, routed)          0.848     0.927    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[12]
    SLICE_X86Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y303        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[12].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.927    
  -------------------------------------------------------------------
                         slack                                  2.098    

Slack (MET) :             2.140ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.885ns  (logic 0.079ns (8.929%)  route 0.806ns (91.071%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y346                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[10]/C
    SLICE_X88Y346        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[10]/Q
                         net (fo=40, routed)          0.806     0.885    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[10]
    SLICE_X87Y322        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X87Y322        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[10].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.885    
  -------------------------------------------------------------------
                         slack                                  2.140    

Slack (MET) :             2.158ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.867ns  (logic 0.079ns (9.112%)  route 0.788ns (90.888%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y337                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[18]/C
    SLICE_X89Y337        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[18]/Q
                         net (fo=3, routed)           0.788     0.867    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[18]
    SLICE_X87Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X87Y316        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[18].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.867    
  -------------------------------------------------------------------
                         slack                                  2.158    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[0]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.407ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.620ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.407ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[7].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.726ns  (logic 0.079ns (4.577%)  route 1.647ns (95.423%))
  Logic Levels:           0  
  Clock Path Skew:        -0.671ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.841ns = ( 6.842 - 3.001 ) 
    Source Clock Delay      (SCD):    4.133ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.937ns (routing 0.696ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.937     4.133    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[7].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X91Y263        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[7].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y263        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[7].u_ddr_mc_rd_en_low/rdEn_reg[1]/Q
                         net (fo=1, routed)           1.647     5.859    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[1]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     6.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.126     6.760 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.082     6.842 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.463    
                         clock uncertainty           -0.170     6.293    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[1])
                                                     -0.027     6.266    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.266    
                         arrival time                          -5.859    
  -------------------------------------------------------------------
                         slack                                  0.407    

Slack (MET) :             0.558ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.431ns  (logic 0.079ns (5.520%)  route 1.352ns (94.480%))
  Logic Levels:           0  
  Clock Path Skew:        -0.674ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.813ns = ( 6.814 - 3.001 ) 
    Source Clock Delay      (SCD):    4.108ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.912ns (routing 0.696ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.912     4.108    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y293        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y293        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[2]/Q
                         net (fo=8, routed)           1.352     5.539    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[2]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.739 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.814 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.435    
                         clock uncertainty           -0.170     6.265    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.168     6.097    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.097    
                         arrival time                          -5.539    
  -------------------------------------------------------------------
                         slack                                  0.558    

Slack (MET) :             0.567ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.465ns  (logic 0.079ns (5.392%)  route 1.386ns (94.608%))
  Logic Levels:           0  
  Clock Path Skew:        -0.655ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.825ns = ( 6.826 - 3.001 ) 
    Source Clock Delay      (SCD):    4.101ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.905ns (routing 0.696ns, distribution 1.209ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.905     4.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y282        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     4.180 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/Q
                         net (fo=8, routed)           1.386     5.566    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[1]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     6.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.751 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.826 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.447    
                         clock uncertainty           -0.170     6.277    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.144     6.133    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.133    
                         arrival time                          -5.566    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.586ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.434ns  (logic 0.079ns (5.508%)  route 1.355ns (94.492%))
  Logic Levels:           0  
  Clock Path Skew:        -0.655ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.825ns = ( 6.826 - 3.001 ) 
    Source Clock Delay      (SCD):    4.101ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.905ns (routing 0.696ns, distribution 1.209ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.905     4.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y282        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.180 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[3]/Q
                         net (fo=8, routed)           1.355     5.535    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     6.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.751 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.826 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.447    
                         clock uncertainty           -0.170     6.277    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.156     6.121    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.121    
                         arrival time                          -5.535    
  -------------------------------------------------------------------
                         slack                                  0.586    

Slack (MET) :             0.594ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.405ns  (logic 0.079ns (5.624%)  route 1.326ns (94.376%))
  Logic Levels:           0  
  Clock Path Skew:        -0.674ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.813ns = ( 6.814 - 3.001 ) 
    Source Clock Delay      (SCD):    4.108ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.912ns (routing 0.696ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.912     4.108    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y293        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y293        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[0]/Q
                         net (fo=8, routed)           1.326     5.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.739 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.814 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.435    
                         clock uncertainty           -0.170     6.265    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     6.107    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.107    
                         arrival time                          -5.512    
  -------------------------------------------------------------------
                         slack                                  0.594    

Slack (MET) :             0.654ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.379ns  (logic 0.079ns (5.729%)  route 1.300ns (94.271%))
  Logic Levels:           0  
  Clock Path Skew:        -0.658ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.822ns = ( 6.823 - 3.001 ) 
    Source Clock Delay      (SCD):    4.101ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.905ns (routing 0.696ns, distribution 1.209ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.905     4.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y282        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.180 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/Q
                         net (fo=8, routed)           1.300     5.480    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.094     6.631    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.748 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.823 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.444    
                         clock uncertainty           -0.170     6.274    
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.140     6.134    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.134    
                         arrival time                          -5.480    
  -------------------------------------------------------------------
                         slack                                  0.654    

Slack (MET) :             0.662ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.374ns  (logic 0.079ns (5.750%)  route 1.295ns (94.250%))
  Logic Levels:           0  
  Clock Path Skew:        -0.655ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.825ns = ( 6.826 - 3.001 ) 
    Source Clock Delay      (SCD):    4.101ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.905ns (routing 0.696ns, distribution 1.209ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.905     4.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y282        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.180 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[0]/Q
                         net (fo=8, routed)           1.295     5.475    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     6.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.751 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.826 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.447    
                         clock uncertainty           -0.170     6.277    
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.140     6.137    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.137    
                         arrival time                          -5.475    
  -------------------------------------------------------------------
                         slack                                  0.662    

Slack (MET) :             0.672ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.392ns  (logic 0.079ns (5.677%)  route 1.313ns (94.323%))
  Logic Levels:           0  
  Clock Path Skew:        -0.674ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.813ns = ( 6.814 - 3.001 ) 
    Source Clock Delay      (SCD):    4.108ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.912ns (routing 0.696ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.912     4.108    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y293        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y293        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_upp_reg[3]/Q
                         net (fo=8, routed)           1.313     5.500    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_upp[3]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.096     6.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.739 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.814 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.435    
                         clock uncertainty           -0.170     6.265    
    BITSLICE_CONTROL_X0Y25
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.172    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.172    
                         arrival time                          -5.500    
  -------------------------------------------------------------------
                         slack                                  0.672    

Slack (MET) :             0.673ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.385ns  (logic 0.079ns (5.705%)  route 1.306ns (94.295%))
  Logic Levels:           0  
  Clock Path Skew:        -0.658ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.822ns = ( 6.823 - 3.001 ) 
    Source Clock Delay      (SCD):    4.101ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.905ns (routing 0.696ns, distribution 1.209ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.905     4.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y282        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.180 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[2]/Q
                         net (fo=8, routed)           1.306     5.485    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[2]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.094     6.631    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.748 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.823 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.444    
                         clock uncertainty           -0.170     6.274    
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[2])
                                                     -0.115     6.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.159    
                         arrival time                          -5.485    
  -------------------------------------------------------------------
                         slack                                  0.673    

Slack (MET) :             0.686ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.343ns  (logic 0.079ns (5.884%)  route 1.264ns (94.116%))
  Logic Levels:           0  
  Clock Path Skew:        -0.658ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.822ns = ( 6.823 - 3.001 ) 
    Source Clock Delay      (SCD):    4.101ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.905ns (routing 0.696ns, distribution 1.209ns)
  Clock Net Delay (Destination): 1.532ns (routing 0.632ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.905     4.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/dReg_reg[10]
    SLICE_X81Y282        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y282        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     4.180 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/oe_low_reg[1]/Q
                         net (fo=8, routed)           1.264     5.444    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_t_b_low[1]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.532     7.167    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.537 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.094     6.631    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.748 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.823 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.379     6.444    
                         clock uncertainty           -0.170     6.274    
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[1])
                                                     -0.144     6.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.130    
                         arrival time                          -5.444    
  -------------------------------------------------------------------
                         slack                                  0.686    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.620ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.319ns  (logic 0.058ns (18.182%)  route 0.261ns (81.818%))
  Logic Levels:           0  
  Clock Path Skew:        -0.512ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.473ns
    Source Clock Delay      (SCD):    4.302ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.668ns (routing 0.632ns, distribution 1.036ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.668     4.302    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X81Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y181        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     4.360 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[1]/Q
                         net (fo=1, routed)           0.261     4.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[1]
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.139     2.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.159 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     3.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.473    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.789    
                         clock uncertainty            0.170     3.959    
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.041     4.000    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.000    
                         arrival time                           4.621    
  -------------------------------------------------------------------
                         slack                                  0.620    

Slack (MET) :             0.631ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.365ns  (logic 0.058ns (15.890%)  route 0.307ns (84.110%))
  Logic Levels:           0  
  Clock Path Skew:        -0.512ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.468ns
    Source Clock Delay      (SCD):    4.296ns
    Clock Pessimism Removal (CPR):    -0.316ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.662ns (routing 0.632ns, distribution 1.030ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.662     4.296    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X82Y198        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y198        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     4.354 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[6].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/Q
                         net (fo=1, routed)           0.307     4.661    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[0]
    BITSLICE_RX_TX_X0Y169
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.134     2.977    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.263 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y26
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     3.425 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.468    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y169
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.316     3.784    
                         clock uncertainty            0.170     3.954    
    BITSLICE_RX_TX_X0Y169
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.076     4.030    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.030    
                         arrival time                           4.661    
  -------------------------------------------------------------------
                         slack                                  0.631    

Slack (MET) :             0.645ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.381ns  (logic 0.058ns (15.223%)  route 0.323ns (84.777%))
  Logic Levels:           0  
  Clock Path Skew:        -0.507ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.485ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.674ns (routing 0.632ns, distribution 1.042ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.674     4.308    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y231        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y231        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     4.366 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           0.323     4.689    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     2.983    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.160 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.269 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.461 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.485    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.801    
                         clock uncertainty            0.170     3.971    
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.073     4.044    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.044    
                         arrival time                           4.689    
  -------------------------------------------------------------------
                         slack                                  0.645    

Slack (MET) :             0.699ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.444ns  (logic 0.059ns (13.288%)  route 0.385ns (86.712%))
  Logic Levels:           0  
  Clock Path Skew:        -0.499ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.485ns
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.667ns (routing 0.632ns, distribution 1.035ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.667     4.301    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y231        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y231        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     4.360 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[4].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           0.385     4.745    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.140     2.983    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.160 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.269 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y30
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.461 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.485    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.801    
                         clock uncertainty            0.170     3.971    
    BITSLICE_RX_TX_X0Y200
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.074     4.045    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.045    
                         arrival time                           4.745    
  -------------------------------------------------------------------
                         slack                                  0.699    

Slack (MET) :             0.702ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.409ns  (logic 0.058ns (14.181%)  route 0.351ns (85.819%))
  Logic Levels:           0  
  Clock Path Skew:        -0.514ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.476ns
    Source Clock Delay      (SCD):    4.307ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.673ns (routing 0.632ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.673     4.307    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y185        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y185        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     4.365 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.351     4.716    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y159
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.139     2.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.159 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.455 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y159
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.792    
                         clock uncertainty            0.170     3.962    
    BITSLICE_RX_TX_X0Y159
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.051     4.013    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.013    
                         arrival time                           4.716    
  -------------------------------------------------------------------
                         slack                                  0.702    

Slack (MET) :             0.706ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.405ns  (logic 0.059ns (14.568%)  route 0.346ns (85.432%))
  Logic Levels:           0  
  Clock Path Skew:        -0.506ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.484ns
    Source Clock Delay      (SCD):    4.307ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.673ns (routing 0.632ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.673     4.307    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y186        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y186        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.366 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.346     4.712    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y161
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.139     2.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.159 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.460 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.484    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y161
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.800    
                         clock uncertainty            0.170     3.970    
    BITSLICE_RX_TX_X0Y161
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.035     4.005    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.005    
                         arrival time                           4.712    
  -------------------------------------------------------------------
                         slack                                  0.706    

Slack (MET) :             0.709ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.406ns  (logic 0.058ns (14.286%)  route 0.348ns (85.714%))
  Logic Levels:           0  
  Clock Path Skew:        -0.514ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.476ns
    Source Clock Delay      (SCD):    4.307ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.673ns (routing 0.632ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.673     4.307    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y186        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y186        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.365 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.348     4.713    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y160
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.139     2.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.159 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     3.454 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     3.476    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y160
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.792    
                         clock uncertainty            0.170     3.962    
    BITSLICE_RX_TX_X0Y160
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.041     4.003    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.003    
                         arrival time                           4.713    
  -------------------------------------------------------------------
                         slack                                  0.709    

Slack (MET) :             0.712ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.410ns  (logic 0.058ns (14.146%)  route 0.352ns (85.854%))
  Logic Levels:           0  
  Clock Path Skew:        -0.517ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.473ns
    Source Clock Delay      (SCD):    4.307ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.673ns (routing 0.632ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.673     4.307    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y185        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y185        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.365 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.352     4.717    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y158
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.139     2.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.159 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     3.455 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     3.473    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y158
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.789    
                         clock uncertainty            0.170     3.959    
    BITSLICE_RX_TX_X0Y158
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.045     4.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.004    
                         arrival time                           4.717    
  -------------------------------------------------------------------
                         slack                                  0.712    

Slack (MET) :             0.719ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.455ns  (logic 0.059ns (12.967%)  route 0.396ns (87.033%))
  Logic Levels:           0  
  Clock Path Skew:        -0.510ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.473ns
    Source Clock Delay      (SCD):    4.299ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.665ns (routing 0.632ns, distribution 1.033ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.665     4.299    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[10]_0
    SLICE_X81Y182        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y182        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.059     4.358 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[0]/Q
                         net (fo=1, routed)           0.396     4.754    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[0]
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.139     2.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.159 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     3.430 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     3.473    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.789    
                         clock uncertainty            0.170     3.959    
    BITSLICE_RX_TX_X0Y156
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.076     4.035    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.035    
                         arrival time                           4.754    
  -------------------------------------------------------------------
                         slack                                  0.719    

Slack (MET) :             0.719ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.398ns  (logic 0.058ns (14.573%)  route 0.340ns (85.427%))
  Logic Levels:           0  
  Clock Path Skew:        -0.506ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.484ns
    Source Clock Delay      (SCD):    4.307ns
    Clock Pessimism Removal (CPR):    -0.317ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.673ns (routing 0.632ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.673     4.307    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y186        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y186        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     4.365 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[7].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.340     4.705    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y161
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.705     3.901    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y7             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.843 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.139     2.982    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.159 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y24
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.460 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.484    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y161
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.317     3.800    
                         clock uncertainty            0.170     3.970    
    BITSLICE_RX_TX_X0Y161
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.015     3.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -3.985    
                         arrival time                           4.705    
  -------------------------------------------------------------------
                         slack                                  0.719    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[1]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.478ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.511ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.478ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.885ns  (logic 0.079ns (4.191%)  route 1.806ns (95.809%))
  Logic Levels:           0  
  Clock Path Skew:        -0.428ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.000ns = ( 7.001 - 3.001 ) 
    Source Clock Delay      (SCD):    4.116ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.920ns (routing 0.696ns, distribution 1.224ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.920     4.116    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X86Y280        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y280        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     4.195 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           1.806     6.001    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     6.682    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.788 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     6.988 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.001    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.312     6.688    
                         clock uncertainty           -0.170     6.518    
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.039     6.479    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.479    
                         arrival time                          -6.001    
  -------------------------------------------------------------------
                         slack                                  0.478    

Slack (MET) :             0.659ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.701ns  (logic 0.079ns (4.644%)  route 1.622ns (95.356%))
  Logic Levels:           0  
  Clock Path Skew:        -0.444ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.006ns = ( 7.007 - 3.001 ) 
    Source Clock Delay      (SCD):    4.071ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.875ns (routing 0.696ns, distribution 1.179ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.875     4.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y192        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y192        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     4.150 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.622     5.772    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     6.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.791 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.866 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.126     6.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.007    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.628    
                         clock uncertainty           -0.170     6.458    
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.027     6.431    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.431    
                         arrival time                          -5.772    
  -------------------------------------------------------------------
                         slack                                  0.659    

Slack (MET) :             0.728ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.509ns  (logic 0.077ns (5.103%)  route 1.432ns (94.897%))
  Logic Levels:           0  
  Clock Path Skew:        -0.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.003ns = ( 7.004 - 3.001 ) 
    Source Clock Delay      (SCD):    4.077ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.881ns (routing 0.696ns, distribution 1.185ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.881     4.077    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X86Y197        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y197        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     4.154 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           1.432     5.586    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     6.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.791 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.866 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     6.991 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.625    
                         clock uncertainty           -0.170     6.455    
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.141     6.314    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.314    
                         arrival time                          -5.586    
  -------------------------------------------------------------------
                         slack                                  0.728    

Slack (MET) :             0.747ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.574ns  (logic 0.079ns (5.019%)  route 1.495ns (94.981%))
  Logic Levels:           0  
  Clock Path Skew:        -0.450ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.006ns = ( 7.007 - 3.001 ) 
    Source Clock Delay      (SCD):    4.077ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.881ns (routing 0.696ns, distribution 1.185ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.881     4.077    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y190        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y190        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.156 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           1.495     5.651    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     6.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.791 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.866 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.126     6.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.007    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.628    
                         clock uncertainty           -0.170     6.458    
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.060     6.398    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.398    
                         arrival time                          -5.651    
  -------------------------------------------------------------------
                         slack                                  0.747    

Slack (MET) :             0.755ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.563ns  (logic 0.076ns (4.862%)  route 1.487ns (95.138%))
  Logic Levels:           0  
  Clock Path Skew:        -0.474ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.003ns = ( 7.004 - 3.001 ) 
    Source Clock Delay      (SCD):    4.098ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.902ns (routing 0.696ns, distribution 1.206ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.902     4.098    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X87Y198        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y198        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.174 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           1.487     5.661    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     6.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.791 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.866 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     6.991 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.004    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.625    
                         clock uncertainty           -0.170     6.455    
    BITSLICE_RX_TX_X0Y257
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.039     6.416    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.416    
                         arrival time                          -5.661    
  -------------------------------------------------------------------
                         slack                                  0.755    

Slack (MET) :             0.767ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.590ns  (logic 0.079ns (4.969%)  route 1.511ns (95.031%))
  Logic Levels:           0  
  Clock Path Skew:        -0.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.006ns = ( 7.007 - 3.001 ) 
    Source Clock Delay      (SCD):    4.078ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.882ns (routing 0.696ns, distribution 1.186ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.882     4.078    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X85Y189        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y189        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.157 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.511     5.668    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     6.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.791 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.866 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.126     6.992 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.007    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.628    
                         clock uncertainty           -0.170     6.458    
    BITSLICE_RX_TX_X0Y258
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.023     6.435    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.435    
                         arrival time                          -5.668    
  -------------------------------------------------------------------
                         slack                                  0.767    

Slack (MET) :             0.776ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.574ns  (logic 0.078ns (4.956%)  route 1.496ns (95.044%))
  Logic Levels:           0  
  Clock Path Skew:        -0.456ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.994ns = ( 6.995 - 3.001 ) 
    Source Clock Delay      (SCD):    4.071ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.875ns (routing 0.696ns, distribution 1.179ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.875     4.071    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y210        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y210        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.149 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.496     5.645    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     6.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.783 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.858 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     6.982 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     6.995    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.616    
                         clock uncertainty           -0.170     6.446    
    BITSLICE_RX_TX_X0Y229
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.025     6.421    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.421    
                         arrival time                          -5.645    
  -------------------------------------------------------------------
                         slack                                  0.776    

Slack (MET) :             0.778ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.561ns  (logic 0.079ns (5.061%)  route 1.482ns (94.939%))
  Logic Levels:           0  
  Clock Path Skew:        -0.453ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.000ns = ( 7.001 - 3.001 ) 
    Source Clock Delay      (SCD):    4.074ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.878ns (routing 0.696ns, distribution 1.182ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.878     4.074    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X88Y210        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y210        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.153 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           1.482     5.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     6.682    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.788 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.863 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y37
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     6.988 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.001    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.622    
                         clock uncertainty           -0.170     6.452    
    BITSLICE_RX_TX_X0Y244
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.039     6.413    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.413    
                         arrival time                          -5.635    
  -------------------------------------------------------------------
                         slack                                  0.778    

Slack (MET) :             0.787ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.543ns  (logic 0.079ns (5.120%)  route 1.464ns (94.880%))
  Logic Levels:           0  
  Clock Path Skew:        -0.472ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.999ns = ( 7.000 - 3.001 ) 
    Source Clock Delay      (SCD):    4.092ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.896ns (routing 0.696ns, distribution 1.200ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.896     4.092    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X84Y201        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y201        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     4.171 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           1.464     5.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y256
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     6.685    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.791 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.866 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     6.988 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.000    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y256
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.621    
                         clock uncertainty           -0.170     6.451    
    BITSLICE_RX_TX_X0Y256
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.028     6.423    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.423    
                         arrival time                          -5.635    
  -------------------------------------------------------------------
                         slack                                  0.787    

Slack (MET) :             0.797ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.526ns  (logic 0.078ns (5.111%)  route 1.448ns (94.889%))
  Logic Levels:           0  
  Clock Path Skew:        -0.444ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.017ns = ( 7.018 - 3.001 ) 
    Source Clock Delay      (SCD):    4.082ns
    Clock Pessimism Removal (CPR):    -0.379ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.886ns (routing 0.696ns, distribution 1.190ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.886     4.082    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X83Y218        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y218        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.160 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[5].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           1.448     5.608    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.575     7.210    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.580 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.100     6.680    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.797 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.872 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y34
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     7.003 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     7.018    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.379     6.639    
                         clock uncertainty           -0.170     6.469    
    BITSLICE_RX_TX_X0Y226
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.064     6.405    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.405    
                         arrival time                          -5.608    
  -------------------------------------------------------------------
                         slack                                  0.797    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.511ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.274ns  (logic 0.058ns (21.168%)  route 0.216ns (78.832%))
  Logic Levels:           0  
  Clock Path Skew:        -0.678ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.350ns
    Source Clock Delay      (SCD):    4.340ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.706ns (routing 0.632ns, distribution 1.074ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.706     4.340    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X82Y292        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y292        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     4.398 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.216     4.614    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.038    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.231 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.312     3.662    
                         clock uncertainty            0.170     3.832    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     4.102    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.102    
                         arrival time                           4.614    
  -------------------------------------------------------------------
                         slack                                  0.511    

Slack (MET) :             0.541ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.303ns  (logic 0.058ns (19.142%)  route 0.245ns (80.858%))
  Logic Levels:           0  
  Clock Path Skew:        -0.675ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.343ns
    Source Clock Delay      (SCD):    4.330ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.696ns (routing 0.632ns, distribution 1.064ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.696     4.330    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y279        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y279        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.388 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.245     4.633    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.141     3.031    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.224 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.343 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.312     3.655    
                         clock uncertainty            0.170     3.825    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     4.092    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.092    
                         arrival time                           4.633    
  -------------------------------------------------------------------
                         slack                                  0.541    

Slack (MET) :             0.555ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.324ns  (logic 0.058ns (17.901%)  route 0.266ns (82.099%))
  Logic Levels:           0  
  Clock Path Skew:        -0.668ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.350ns
    Source Clock Delay      (SCD):    4.330ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.696ns (routing 0.632ns, distribution 1.064ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.696     4.330    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y279        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y279        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     4.388 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.266     4.654    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.038    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.231 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.312     3.662    
                         clock uncertainty            0.170     3.832    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     4.099    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.099    
                         arrival time                           4.654    
  -------------------------------------------------------------------
                         slack                                  0.555    

Slack (MET) :             0.577ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.295ns  (logic 0.058ns (19.661%)  route 0.237ns (80.339%))
  Logic Levels:           0  
  Clock Path Skew:        -0.688ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.350ns
    Source Clock Delay      (SCD):    4.350ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.716ns (routing 0.632ns, distribution 1.084ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.716     4.350    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X83Y290        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y290        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     4.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[1]/Q
                         net (fo=1, routed)           0.237     4.645    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[1]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.038    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.231 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.350 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.313     3.662    
                         clock uncertainty            0.170     3.832    
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[1])
                                                      0.236     4.068    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.068    
                         arrival time                           4.645    
  -------------------------------------------------------------------
                         slack                                  0.577    

Slack (MET) :             0.578ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.307ns  (logic 0.058ns (18.893%)  route 0.249ns (81.108%))
  Logic Levels:           0  
  Clock Path Skew:        -0.677ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.343ns
    Source Clock Delay      (SCD):    4.332ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.698ns (routing 0.632ns, distribution 1.066ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.698     4.332    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X81Y279        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y279        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     4.390 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[1]/Q
                         net (fo=1, routed)           0.249     4.639    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[1]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.141     3.031    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.224 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.343 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.312     3.655    
                         clock uncertainty            0.170     3.825    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[1])
                                                      0.236     4.061    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.061    
                         arrival time                           4.639    
  -------------------------------------------------------------------
                         slack                                  0.578    

Slack (MET) :             0.603ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.280ns  (logic 0.058ns (20.714%)  route 0.222ns (79.286%))
  Logic Levels:           0  
  Clock Path Skew:        -0.720ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.308ns
    Source Clock Delay      (SCD):    4.340ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.706ns (routing 0.632ns, distribution 1.074ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.706     4.340    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rsMask_reg[7][9]_0
    SLICE_X83Y266        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y266        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     4.398 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.222     4.620    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.138     3.028    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     3.190 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     3.308 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.313     3.620    
                         clock uncertainty            0.170     3.790    
    BITSLICE_CONTROL_X0Y35
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.227     4.017    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.017    
                         arrival time                           4.620    
  -------------------------------------------------------------------
                         slack                                  0.603    

Slack (MET) :             0.608ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.326ns  (logic 0.058ns (17.791%)  route 0.268ns (82.209%))
  Logic Levels:           0  
  Clock Path Skew:        -0.488ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.540ns
    Source Clock Delay      (SCD):    4.340ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.706ns (routing 0.632ns, distribution 1.074ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.706     4.340    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[10]_0
    SLICE_X82Y291        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y291        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     4.398 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[1].u_ddr_mc_wr_byte/genBit[0].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.268     4.666    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     3.038    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.215 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.324 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y38
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.516 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.312     3.852    
                         clock uncertainty            0.170     4.022    
    BITSLICE_RX_TX_X0Y252
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.035     4.057    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.057    
                         arrival time                           4.666    
  -------------------------------------------------------------------
                         slack                                  0.608    

Slack (MET) :             0.609ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.351ns  (logic 0.058ns (16.524%)  route 0.293ns (83.476%))
  Logic Levels:           0  
  Clock Path Skew:        -0.696ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.343ns
    Source Clock Delay      (SCD):    4.351ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.717ns (routing 0.632ns, distribution 1.085ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.717     4.351    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X83Y290        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y290        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.058     4.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.293     4.702    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.141     3.031    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.224 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.343 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.313     3.655    
                         clock uncertainty            0.170     3.825    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     4.093    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.093    
                         arrival time                           4.702    
  -------------------------------------------------------------------
                         slack                                  0.609    

Slack (MET) :             0.634ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.348ns  (logic 0.058ns (16.667%)  route 0.290ns (83.333%))
  Logic Levels:           0  
  Clock Path Skew:        -0.678ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.320ns
    Source Clock Delay      (SCD):    4.310ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.676ns (routing 0.632ns, distribution 1.044ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.676     4.310    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[6][9]_0
    SLICE_X81Y270        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y270        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.368 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.290     4.658    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[2]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.150     3.040    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     3.202 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     3.320 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.312     3.632    
                         clock uncertainty            0.170     3.802    
    BITSLICE_CONTROL_X0Y39
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.222     4.024    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.024    
                         arrival time                           4.658    
  -------------------------------------------------------------------
                         slack                                  0.634    

Slack (MET) :             0.643ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.387ns  (logic 0.058ns (14.987%)  route 0.329ns (85.013%))
  Logic Levels:           0  
  Clock Path Skew:        -0.696ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.343ns
    Source Clock Delay      (SCD):    4.351ns
    Clock Pessimism Removal (CPR):    -0.313ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.717ns (routing 0.632ns, distribution 1.085ns)
  Clock Net Delay (Destination): 1.752ns (routing 0.696ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.717     4.351    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X83Y290        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y290        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     4.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[0].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.329     4.738    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.752     3.948    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y8             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.890 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.141     3.031    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     3.224 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     3.343 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.313     3.655    
                         clock uncertainty            0.170     3.825    
    BITSLICE_CONTROL_X0Y36
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     4.095    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -4.095    
                         arrival time                           4.738    
  -------------------------------------------------------------------
                         slack                                  0.643    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[2]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.691ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.567ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.691ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][26]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.706ns  (logic 0.080ns (4.690%)  route 1.626ns (95.310%))
  Logic Levels:           0  
  Clock Path Skew:        -0.420ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.016ns = ( 7.017 - 3.001 ) 
    Source Clock Delay      (SCD):    4.130ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.934ns (routing 0.696ns, distribution 1.238ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.934     4.130    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y341        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.210 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][26]/Q
                         net (fo=2, routed)           1.626     5.836    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[2]
    BITSLICE_RX_TX_X0Y296
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.102     6.698    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.804 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.879 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.125     7.004 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     7.017    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y296
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.306     6.710    
                         clock uncertainty           -0.170     6.540    
    BITSLICE_RX_TX_X0Y296
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.013     6.527    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.527    
                         arrival time                          -5.836    
  -------------------------------------------------------------------
                         slack                                  0.691    

Slack (MET) :             0.790ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.397ns  (logic 0.079ns (5.657%)  route 1.318ns (94.343%))
  Logic Levels:           0  
  Clock Path Skew:        -0.551ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.873ns = ( 6.874 - 3.001 ) 
    Source Clock Delay      (SCD):    4.118ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.922ns (routing 0.696ns, distribution 1.226ns)
  Clock Net Delay (Destination): 1.591ns (routing 0.632ns, distribution 0.959ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.922     4.118    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y338        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.197 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/Q
                         net (fo=6, routed)           1.318     5.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.097     6.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.799 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.874 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.306     6.567    
                         clock uncertainty           -0.170     6.397    
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.304    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.304    
                         arrival time                          -5.514    
  -------------------------------------------------------------------
                         slack                                  0.790    

Slack (MET) :             0.803ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.389ns  (logic 0.079ns (5.689%)  route 1.310ns (94.311%))
  Logic Levels:           0  
  Clock Path Skew:        -0.546ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.878ns = ( 6.879 - 3.001 ) 
    Source Clock Delay      (SCD):    4.118ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.922ns (routing 0.696ns, distribution 1.226ns)
  Clock Net Delay (Destination): 1.591ns (routing 0.632ns, distribution 0.959ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.922     4.118    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y338        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.197 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/Q
                         net (fo=6, routed)           1.310     5.507    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.102     6.698    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.804 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.879 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.306     6.572    
                         clock uncertainty           -0.170     6.402    
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.093     6.309    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.309    
                         arrival time                          -5.507    
  -------------------------------------------------------------------
                         slack                                  0.803    

Slack (MET) :             0.846ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.508ns  (logic 0.078ns (5.173%)  route 1.430ns (94.827%))
  Logic Levels:           0  
  Clock Path Skew:        -0.420ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.013ns = ( 7.014 - 3.001 ) 
    Source Clock Delay      (SCD):    4.127ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.931ns (routing 0.696ns, distribution 1.235ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.931     4.127    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X86Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y324        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.205 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][2]/Q
                         net (fo=2, routed)           1.430     5.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_BA[1]
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.097     6.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.799 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.874 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     6.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     7.014    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.306     6.707    
                         clock uncertainty           -0.170     6.537    
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.056     6.481    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.481    
                         arrival time                          -5.635    
  -------------------------------------------------------------------
                         slack                                  0.846    

Slack (MET) :             0.850ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.492ns  (logic 0.079ns (5.295%)  route 1.413ns (94.705%))
  Logic Levels:           0  
  Clock Path Skew:        -0.448ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.013ns = ( 7.014 - 3.001 ) 
    Source Clock Delay      (SCD):    4.155ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.959ns (routing 0.696ns, distribution 1.263ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.959     4.155    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X84Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/Q
                         net (fo=2, routed)           1.413     5.647    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[2]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.097     6.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.799 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.874 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.126     7.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.014    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.306     6.707    
                         clock uncertainty           -0.170     6.537    
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.040     6.497    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.497    
                         arrival time                          -5.647    
  -------------------------------------------------------------------
                         slack                                  0.850    

Slack (MET) :             0.851ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.533ns  (logic 0.078ns (5.088%)  route 1.455ns (94.912%))
  Logic Levels:           0  
  Clock Path Skew:        -0.420ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.013ns = ( 7.014 - 3.001 ) 
    Source Clock Delay      (SCD):    4.127ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.931ns (routing 0.696ns, distribution 1.235ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.931     4.127    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X86Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y324        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.205 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][4]/Q
                         net (fo=2, routed)           1.455     5.660    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_BA[4]
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.097     6.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.799 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.874 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     6.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     7.014    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.306     6.707    
                         clock uncertainty           -0.170     6.537    
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.026     6.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.511    
                         arrival time                          -5.660    
  -------------------------------------------------------------------
                         slack                                  0.851    

Slack (MET) :             0.858ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.519ns  (logic 0.078ns (5.135%)  route 1.441ns (94.865%))
  Logic Levels:           0  
  Clock Path Skew:        -0.420ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.013ns = ( 7.014 - 3.001 ) 
    Source Clock Delay      (SCD):    4.127ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.931ns (routing 0.696ns, distribution 1.235ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.931     4.127    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X86Y324        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y324        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     4.205 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][4]/Q
                         net (fo=2, routed)           1.441     5.646    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_BA[3]
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.097     6.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.799 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.874 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.125     6.999 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     7.014    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.306     6.707    
                         clock uncertainty           -0.170     6.537    
    BITSLICE_RX_TX_X0Y280
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.033     6.504    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.504    
                         arrival time                          -5.646    
  -------------------------------------------------------------------
                         slack                                  0.858    

Slack (MET) :             0.862ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.280ns  (logic 0.079ns (6.173%)  route 1.201ns (93.827%))
  Logic Levels:           0  
  Clock Path Skew:        -0.533ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.891ns = ( 6.892 - 3.001 ) 
    Source Clock Delay      (SCD):    4.118ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.922ns (routing 0.696ns, distribution 1.226ns)
  Clock Net Delay (Destination): 1.591ns (routing 0.632ns, distribution 0.959ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.922     4.118    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y338        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.197 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[3]/Q
                         net (fo=6, routed)           1.201     5.398    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[3]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.104     6.700    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.817 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.892 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.306     6.585    
                         clock uncertainty           -0.170     6.415    
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[3])
                                                     -0.156     6.259    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          6.259    
                         arrival time                          -5.398    
  -------------------------------------------------------------------
                         slack                                  0.862    

Slack (MET) :             0.871ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.435ns  (logic 0.078ns (5.436%)  route 1.357ns (94.564%))
  Logic Levels:           0  
  Clock Path Skew:        -0.471ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.031ns = ( 7.032 - 3.001 ) 
    Source Clock Delay      (SCD):    4.136ns
    Clock Pessimism Removal (CPR):    -0.366ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.940ns (routing 0.696ns, distribution 1.244ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.940     4.136    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X89Y244        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y244        FDSE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.214 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][7]/Q
                         net (fo=1, routed)           1.357     5.571    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ACT_n[7]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.104     6.700    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     6.817 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.892 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.128     7.020 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     7.032    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.366     6.665    
                         clock uncertainty           -0.170     6.495    
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.053     6.442    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.442    
                         arrival time                          -5.571    
  -------------------------------------------------------------------
                         slack                                  0.871    

Slack (MET) :             0.885ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[2]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.456ns  (logic 0.079ns (5.426%)  route 1.377ns (94.574%))
  Logic Levels:           0  
  Clock Path Skew:        -0.448ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.013ns = ( 7.014 - 3.001 ) 
    Source Clock Delay      (SCD):    4.155ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.959ns (routing 0.696ns, distribution 1.263ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.959     4.155    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X84Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y320        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.234 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][10]/Q
                         net (fo=2, routed)           1.377     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[1]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      3.001     3.001 f  
    J19                                               0.000     3.001 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     3.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     3.555 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.595 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     3.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.916 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     4.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.396 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.635 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.591     7.226    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     6.596 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.097     6.693    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     6.799 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     6.874 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.126     7.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     7.014    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.306     6.707    
                         clock uncertainty           -0.170     6.537    
    BITSLICE_RX_TX_X0Y279
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.041     6.496    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          6.496    
                         arrival time                          -5.611    
  -------------------------------------------------------------------
                         slack                                  0.885    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.567ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.327ns  (logic 0.058ns (17.736%)  route 0.269ns (82.264%))
  Logic Levels:           0  
  Clock Path Skew:        -0.483ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.555ns
    Source Clock Delay      (SCD):    4.344ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.710ns (routing 0.632ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.710     4.344    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     4.402 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][68]/Q
                         net (fo=2, routed)           0.269     4.671    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.053    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.230 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.339 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.531 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.861    
                         clock uncertainty            0.170     4.031    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.073     4.104    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.104    
                         arrival time                           4.671    
  -------------------------------------------------------------------
                         slack                                  0.567    

Slack (MET) :             0.571ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][74]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.309ns  (logic 0.060ns (19.398%)  route 0.249ns (80.602%))
  Logic Levels:           0  
  Clock Path Skew:        -0.488ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.547ns
    Source Clock Delay      (SCD):    4.341ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.707ns (routing 0.632ns, distribution 1.075ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.707     4.341    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y335        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][74]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y335        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     4.401 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][74]/Q
                         net (fo=2, routed)           0.249     4.651    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[2]
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.053    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.230 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.339 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     3.525 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     3.547    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.853    
                         clock uncertainty            0.170     4.023    
    BITSLICE_RX_TX_X0Y290
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                      0.056     4.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.079    
                         arrival time                           4.651    
  -------------------------------------------------------------------
                         slack                                  0.571    

Slack (MET) :             0.582ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.343ns  (logic 0.060ns (17.485%)  route 0.283ns (82.515%))
  Logic Levels:           0  
  Clock Path Skew:        -0.483ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.555ns
    Source Clock Delay      (SCD):    4.344ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.710ns (routing 0.632ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.710     4.344    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.060     4.404 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][70]/Q
                         net (fo=2, routed)           0.283     4.687    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[5]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.053    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.230 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.339 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.531 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.861    
                         clock uncertainty            0.170     4.031    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.074     4.105    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.105    
                         arrival time                           4.687    
  -------------------------------------------------------------------
                         slack                                  0.582    

Slack (MET) :             0.587ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][87]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.061ns (19.614%)  route 0.250ns (80.386%))
  Logic Levels:           0  
  Clock Path Skew:        -0.487ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.547ns
    Source Clock Delay      (SCD):    4.340ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.706ns (routing 0.632ns, distribution 1.074ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.706     4.340    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y334        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][87]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y334        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     4.401 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][87]/Q
                         net (fo=1, routed)           0.250     4.651    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.053    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.230 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.339 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.526 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.547    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.853    
                         clock uncertainty            0.170     4.023    
    BITSLICE_RX_TX_X0Y289
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.041     4.064    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.064    
                         arrival time                           4.651    
  -------------------------------------------------------------------
                         slack                                  0.587    

Slack (MET) :             0.588ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][100]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.315ns  (logic 0.058ns (18.395%)  route 0.257ns (81.605%))
  Logic Levels:           0  
  Clock Path Skew:        -0.496ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.549ns
    Source Clock Delay      (SCD):    4.351ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.717ns (routing 0.632ns, distribution 1.085ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.717     4.351    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][100]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y319        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     4.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][100]/Q
                         net (fo=2, routed)           0.257     4.666    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y276
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.143     3.055    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.232 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.341 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.528 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.549    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y276
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.855    
                         clock uncertainty            0.170     4.025    
    BITSLICE_RX_TX_X0Y276
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.053     4.078    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.078    
                         arrival time                           4.666    
  -------------------------------------------------------------------
                         slack                                  0.588    

Slack (MET) :             0.593ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][0]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.325ns  (logic 0.058ns (17.846%)  route 0.267ns (82.154%))
  Logic Levels:           0  
  Clock Path Skew:        -0.490ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.554ns
    Source Clock Delay      (SCD):    4.350ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.716ns (routing 0.632ns, distribution 1.084ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.716     4.350    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y349        FDSE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y349        FDSE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     4.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ACT_n_dly_reg[0][0]/Q
                         net (fo=1, routed)           0.267     4.675    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ACT_n[0]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.148     3.060    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.237 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.346 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     3.533 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.554    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.860    
                         clock uncertainty            0.170     4.030    
    BITSLICE_RX_TX_X0Y302
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.052     4.082    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.082    
                         arrival time                           4.675    
  -------------------------------------------------------------------
                         slack                                  0.593    

Slack (MET) :             0.598ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][66]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.308ns  (logic 0.060ns (19.457%)  route 0.248ns (80.543%))
  Logic Levels:           0  
  Clock Path Skew:        -0.483ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.555ns
    Source Clock Delay      (SCD):    4.344ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.710ns (routing 0.632ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.710     4.344    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][66]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.060     4.404 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][66]/Q
                         net (fo=2, routed)           0.248     4.653    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[2]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.053    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.230 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.339 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.531 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.861    
                         clock uncertainty            0.170     4.031    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                      0.023     4.054    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.054    
                         arrival time                           4.653    
  -------------------------------------------------------------------
                         slack                                  0.598    

Slack (MET) :             0.599ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][66]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.321ns  (logic 0.060ns (18.670%)  route 0.261ns (81.330%))
  Logic Levels:           0  
  Clock Path Skew:        -0.483ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.555ns
    Source Clock Delay      (SCD):    4.344ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.710ns (routing 0.632ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.710     4.344    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y336        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][66]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y336        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.060     4.404 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][66]/Q
                         net (fo=2, routed)           0.261     4.666    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[1]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 f  
    J19                                               0.000     0.000 f  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.141     3.053    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.230 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.339 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y44
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     3.531 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     3.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.861    
                         clock uncertainty            0.170     4.031    
    BITSLICE_RX_TX_X0Y291
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.035     4.066    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.066    
                         arrival time                           4.666    
  -------------------------------------------------------------------
                         slack                                  0.599    

Slack (MET) :             0.600ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.328ns  (logic 0.059ns (17.988%)  route 0.269ns (82.012%))
  Logic Levels:           0  
  Clock Path Skew:        -0.527ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.516ns
    Source Clock Delay      (SCD):    4.349ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.715ns (routing 0.632ns, distribution 1.083ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.715     4.349    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X82Y341        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y341        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.059     4.408 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][39]/Q
                         net (fo=1, routed)           0.269     4.677    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.146     3.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     3.209 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.318 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y45
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.177     3.495 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     3.516    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.822    
                         clock uncertainty            0.170     3.992    
    BITSLICE_RX_TX_X0Y295
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.084     4.076    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[10].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.076    
                         arrival time                           4.677    
  -------------------------------------------------------------------
                         slack                                  0.600    

Slack (MET) :             0.601ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][132]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[2]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[2]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[2]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.059ns (18.910%)  route 0.253ns (81.090%))
  Logic Levels:           0  
  Clock Path Skew:        -0.489ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.555ns
    Source Clock Delay      (SCD):    4.350ns
    Clock Pessimism Removal (CPR):    -0.306ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.716ns (routing 0.632ns, distribution 1.084ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.716     4.350    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][132]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y347        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.059     4.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][132]/Q
                         net (fo=1, routed)           0.253     4.662    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[4]
    BITSLICE_RX_TX_X0Y300
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[2]_DIV rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=41413, routed)       1.774     3.970    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y10            PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     2.912 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[2].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=6, routed)           0.148     3.060    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     3.237 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     3.346 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.186     3.532 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.023     3.555    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y300
                         RXTX_BITSLICE                                r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.306     3.861    
                         clock uncertainty            0.170     4.031    
    BITSLICE_RX_TX_X0Y300
                         RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                      0.029     4.060    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -4.060    
                         arrival time                           4.662    
  -------------------------------------------------------------------
                         slack                                  0.601    





---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       49.425ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             49.425ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.600ns  (logic 0.079ns (13.167%)  route 0.521ns (86.833%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X88Y362        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.521     0.600    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X95Y361        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X95Y361        FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.600    
  -------------------------------------------------------------------
                         slack                                 49.425    

Slack (MET) :             49.482ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.543ns  (logic 0.078ns (14.365%)  route 0.465ns (85.635%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y362                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X87Y362        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.465     0.543    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X95Y361        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X95Y361        FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.543    
  -------------------------------------------------------------------
                         slack                                 49.482    

Slack (MET) :             49.509ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.516ns  (logic 0.079ns (15.310%)  route 0.437ns (84.690%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X88Y362        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.437     0.516    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X95Y361        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X95Y361        FDCE (Setup_FFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.516    
  -------------------------------------------------------------------
                         slack                                 49.509    

Slack (MET) :             49.647ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.378ns  (logic 0.079ns (20.899%)  route 0.299ns (79.101%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y366                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X83Y366        FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.299     0.378    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X81Y366        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X81Y366        FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.378    
  -------------------------------------------------------------------
                         slack                                 49.647    

Slack (MET) :             49.687ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.338ns  (logic 0.080ns (23.669%)  route 0.258ns (76.331%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y365                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X83Y365        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.258     0.338    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X82Y366        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X82Y366        FDCE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.338    
  -------------------------------------------------------------------
                         slack                                 49.687    

Slack (MET) :             49.707ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.318ns  (logic 0.078ns (24.528%)  route 0.240ns (75.472%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y365                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X83Y365        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.240     0.318    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X82Y366        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X82Y366        FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.318    
  -------------------------------------------------------------------
                         slack                                 49.707    

Slack (MET) :             49.719ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.306ns  (logic 0.078ns (25.490%)  route 0.228ns (74.510%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y365                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X83Y365        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.228     0.306    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X82Y366        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X82Y366        FDCE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.306    
  -------------------------------------------------------------------
                         slack                                 49.719    

Slack (MET) :             49.745ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.280ns  (logic 0.079ns (28.214%)  route 0.201ns (71.786%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X88Y362        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.201     0.280    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X88Y362        FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.280    
  -------------------------------------------------------------------
                         slack                                 49.745    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       11.507ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.507ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.518ns  (logic 0.081ns (15.637%)  route 0.437ns (84.363%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
    SLICE_X84Y358        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.437     0.518    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X82Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X82Y359        FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.518    
  -------------------------------------------------------------------
                         slack                                 11.507    

Slack (MET) :             11.524ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.501ns  (logic 0.079ns (15.768%)  route 0.422ns (84.232%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
    SLICE_X84Y358        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.422     0.501    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X85Y359        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.501    
  -------------------------------------------------------------------
                         slack                                 11.524    

Slack (MET) :             11.539ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.486ns  (logic 0.080ns (16.460%)  route 0.406ns (83.540%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
    SLICE_X82Y358        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.406     0.486    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X85Y359        FDRE (Setup_DFF_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.486    
  -------------------------------------------------------------------
                         slack                                 11.539    

Slack (MET) :             11.622ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.403ns  (logic 0.079ns (19.603%)  route 0.324ns (80.397%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y354                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
    SLICE_X85Y354        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.324     0.403    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X85Y359        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.403    
  -------------------------------------------------------------------
                         slack                                 11.622    

Slack (MET) :             11.658ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.367ns  (logic 0.079ns (21.526%)  route 0.288ns (78.474%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
    SLICE_X84Y358        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.288     0.367    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X84Y358        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.367    
  -------------------------------------------------------------------
                         slack                                 11.658    

Slack (MET) :             11.735ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.290ns  (logic 0.078ns (26.897%)  route 0.212ns (73.103%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
    SLICE_X86Y358        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.212     0.290    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X85Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X85Y358        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.290    
  -------------------------------------------------------------------
                         slack                                 11.735    

Slack (MET) :             11.738ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.287ns  (logic 0.079ns (27.526%)  route 0.208ns (72.474%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y355                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
    SLICE_X84Y355        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.208     0.287    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X84Y356        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.287    
  -------------------------------------------------------------------
                         slack                                 11.738    

Slack (MET) :             11.747ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.278ns  (logic 0.079ns (28.417%)  route 0.199ns (71.583%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
    SLICE_X84Y358        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.199     0.278    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X83Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X83Y359        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.278    
  -------------------------------------------------------------------
                         slack                                 11.747    

Slack (MET) :             11.788ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.237ns  (logic 0.081ns (34.177%)  route 0.156ns (65.823%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
    SLICE_X84Y358        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.156     0.237    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X83Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X83Y357        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.237    
  -------------------------------------------------------------------
                         slack                                 11.788    

Slack (MET) :             11.790ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.235ns  (logic 0.079ns (33.617%)  route 0.156ns (66.383%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y354                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
    SLICE_X84Y354        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.156     0.235    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X84Y356        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.235    
  -------------------------------------------------------------------
                         slack                                 11.790    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        1.247ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.249ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.247ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout0 rise@3.001ns)
  Data Path Delay:        1.365ns  (logic 0.079ns (5.788%)  route 1.286ns (94.212%))
  Logic Levels:           0  
  Clock Path Skew:        -0.225ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.380ns = ( 10.381 - 6.001 ) 
    Source Clock Delay      (SCD):    4.133ns = ( 7.133 - 3.001 ) 
    Clock Pessimism Removal (CPR):    -0.472ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.937ns (routing 0.696ns, distribution 1.241ns)
  Clock Net Delay (Destination): 1.733ns (routing 0.644ns, distribution 1.089ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    J19                                               0.000     3.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     3.101    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     3.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     3.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     4.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     5.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     4.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     5.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.937     7.133    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y308        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     7.212 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           1.286     8.498    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts
    SLICE_X86Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    J19                                               0.000     6.001 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     6.080    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     6.555 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.595    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.595 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     6.892    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     6.916 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     7.766    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     8.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     8.624    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.733    10.381    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X86Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism             -0.472     9.909    
                         clock uncertainty           -0.188     9.720    
    SLICE_X86Y314        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025     9.745    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                          9.745    
                         arrival time                          -8.498    
  -------------------------------------------------------------------
                         slack                                  1.247    

Slack (MET) :             3.216ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        1.809ns  (logic 0.078ns (4.312%)  route 1.731ns (95.688%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y308                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[15]/C
    SLICE_X87Y308        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[15]/Q
                         net (fo=1, routed)           1.731     1.809    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[15]
    SLICE_X86Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X86Y315        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[15].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -1.809    
  -------------------------------------------------------------------
                         slack                                  3.216    

Slack (MET) :             3.479ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        1.546ns  (logic 0.081ns (5.239%)  route 1.465ns (94.761%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y313                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/C
    SLICE_X85Y313        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/Q
                         net (fo=1, routed)           1.465     1.546    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X86Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X86Y314        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -1.546    
  -------------------------------------------------------------------
                         slack                                  3.479    

Slack (MET) :             4.232ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.793ns  (logic 0.080ns (10.088%)  route 0.713ns (89.912%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y305                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/C
    SLICE_X87Y305        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[20]/Q
                         net (fo=1, routed)           0.713     0.793    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[20]
    SLICE_X86Y315        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X86Y315        FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[20].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.793    
  -------------------------------------------------------------------
                         slack                                  4.232    

Slack (MET) :             4.316ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[28].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.709ns  (logic 0.079ns (11.142%)  route 0.630ns (88.858%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y306                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[28]/C
    SLICE_X90Y306        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[28]/Q
                         net (fo=1, routed)           0.630     0.709    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[28]
    SLICE_X87Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[28].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X87Y347        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[28].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.709    
  -------------------------------------------------------------------
                         slack                                  4.316    

Slack (MET) :             4.374ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.651ns  (logic 0.079ns (12.135%)  route 0.572ns (87.865%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y306                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/C
    SLICE_X90Y306        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[29]/Q
                         net (fo=1, routed)           0.572     0.651    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[29]
    SLICE_X87Y347        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X87Y347        FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[29].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.651    
  -------------------------------------------------------------------
                         slack                                  4.374    

Slack (MET) :             4.414ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.611ns  (logic 0.081ns (13.257%)  route 0.530ns (86.743%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y303                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/C
    SLICE_X88Y303        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/Q
                         net (fo=1, routed)           0.530     0.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[11]
    SLICE_X88Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X88Y332        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.611    
  -------------------------------------------------------------------
                         slack                                  4.414    

Slack (MET) :             4.455ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.570ns  (logic 0.079ns (13.860%)  route 0.491ns (86.140%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y308                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
    SLICE_X87Y308        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/Q
                         net (fo=1, routed)           0.491     0.570    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[17]
    SLICE_X87Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X87Y320        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.570    
  -------------------------------------------------------------------
                         slack                                  4.455    

Slack (MET) :             4.498ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.527ns  (logic 0.080ns (15.180%)  route 0.447ns (84.820%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y317                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/C
    SLICE_X84Y317        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[3]/Q
                         net (fo=1, routed)           0.447     0.527    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[3]
    SLICE_X84Y317        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X84Y317        FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.527    
  -------------------------------------------------------------------
                         slack                                  4.498    

Slack (MET) :             4.541ns  (required time - arrival time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.484ns  (logic 0.081ns (16.736%)  route 0.403ns (83.264%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y310                                     0.000     0.000 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/C
    SLICE_X88Y310        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/Q
                         net (fo=1, routed)           0.403     0.484    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[27]
    SLICE_X88Y332        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X88Y332        FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.484    
  -------------------------------------------------------------------
                         slack                                  4.541    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.249ns  (arrival time - required time)
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.668ns  (logic 0.039ns (5.838%)  route 0.629ns (94.162%))
  Logic Levels:           0  
  Clock Path Skew:        0.185ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.513ns
    Source Clock Delay      (SCD):    2.615ns
    Clock Pessimism Removal (CPR):    -0.286ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.068ns (routing 0.385ns, distribution 0.683ns)
  Clock Net Delay (Destination): 1.219ns (routing 0.439ns, distribution 0.780ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.068     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y308        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.654 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.629     3.283    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts
    SLICE_X86Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.219     2.513    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X86Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism              0.286     2.799    
                         clock uncertainty            0.188     2.988    
    SLICE_X86Y314        FDRE (Hold_EFF_SLICEM_C_D)
                                                      0.046     3.034    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         -3.034    
                         arrival time                           3.283    
  -------------------------------------------------------------------
                         slack                                  0.249    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Setup :            0  Failing Endpoints,  Worst Slack        0.636ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.229ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.636ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_7/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        1.006ns  (logic 0.077ns (7.657%)  route 0.929ns (92.343%))
  Logic Levels:           0  
  Clock Path Skew:        -0.194ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.533ns = ( 8.486 - 1.953 ) 
    Source Clock Delay      (SCD):    6.661ns
    Clock Pessimism Removal (CPR):    -0.066ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.159ns (routing 1.562ns, distribution 1.597ns)
  Clock Net Delay (Destination): 2.730ns (routing 1.417ns, distribution 1.313ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.159     6.661    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X97Y225        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_7/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y225        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     6.738 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_7/Q
                         net (fo=109, routed)         0.929     7.667    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_7_alias
    SLICE_X85Y217        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.730     8.486    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X85Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.066     8.420    
                         clock uncertainty           -0.051     8.369    
    SLICE_X85Y217        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     8.303    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          8.303    
                         arrival time                          -7.667    
  -------------------------------------------------------------------
                         slack                                  0.636    

Slack (MET) :             0.812ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.963ns  (logic 0.079ns (8.204%)  route 0.884ns (91.796%))
  Logic Levels:           0  
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.444ns = ( 8.397 - 1.953 ) 
    Source Clock Delay      (SCD):    6.424ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.922ns (routing 1.562ns, distribution 1.360ns)
  Clock Net Delay (Destination): 2.641ns (routing 1.417ns, distribution 1.224ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.922     6.424    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X67Y199        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y199        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     6.503 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                         net (fo=260, routed)         0.884     7.387    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_2_alias
    SLICE_X79Y217        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.641     8.397    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X79Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.080     8.317    
                         clock uncertainty           -0.051     8.266    
    SLICE_X79Y217        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066     8.200    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          8.200    
                         arrival time                          -7.387    
  -------------------------------------------------------------------
                         slack                                  0.812    

Slack (MET) :             0.812ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.963ns  (logic 0.079ns (8.204%)  route 0.884ns (91.796%))
  Logic Levels:           0  
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.444ns = ( 8.397 - 1.953 ) 
    Source Clock Delay      (SCD):    6.424ns
    Clock Pessimism Removal (CPR):    -0.080ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.922ns (routing 1.562ns, distribution 1.360ns)
  Clock Net Delay (Destination): 2.641ns (routing 1.417ns, distribution 1.224ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.922     6.424    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X67Y199        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y199        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     6.503 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                         net (fo=260, routed)         0.884     7.387    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_2_alias
    SLICE_X79Y217        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.641     8.397    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X79Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism             -0.080     8.317    
                         clock uncertainty           -0.051     8.266    
    SLICE_X79Y217        FDCE (Recov_AFF2_SLICEM_C_CLR)
                                                     -0.066     8.200    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          8.200    
                         arrival time                          -7.387    
  -------------------------------------------------------------------
                         slack                                  0.812    

Slack (MET) :             1.045ns  (required time - arrival time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            1.953ns  (clk_out1_d_1_clk_adc0_x2_0 rise@1.953ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.550ns  (logic 0.077ns (13.999%)  route 0.473ns (86.001%))
  Logic Levels:           0  
  Clock Path Skew:        -0.241ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.544ns = ( 8.497 - 1.953 ) 
    Source Clock Delay      (SCD):    6.629ns
    Clock Pessimism Removal (CPR):    -0.156ns
  Clock Uncertainty:      0.051ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.074ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.127ns (routing 1.562ns, distribution 1.565ns)
  Clock Net Delay (Destination): 2.741ns (routing 1.417ns, distribution 1.324ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.127     6.629    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X96Y240        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y240        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     6.706 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=188, routed)         0.473     7.179    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_14_alias
    SLICE_X85Y229        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      1.953     1.953 r  
    HSADC_X0Y0           HSADC                        0.000     1.953 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     2.075 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     2.225    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.339 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     4.888    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     5.518 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     5.732    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     5.756 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.741     8.497    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X85Y229        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism             -0.156     8.341    
                         clock uncertainty           -0.051     8.290    
    SLICE_X85Y229        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     8.224    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                          8.224    
                         arrival time                          -7.179    
  -------------------------------------------------------------------
                         slack                                  1.045    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.229ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.271ns  (logic 0.039ns (14.408%)  route 0.232ns (85.592%))
  Logic Levels:           0  
  Clock Path Skew:        0.062ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.849ns
    Source Clock Delay      (SCD):    3.924ns
    Clock Pessimism Removal (CPR):    -0.137ns
  Clock Net Delay (Source):      1.718ns (routing 0.858ns, distribution 0.860ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.956ns, distribution 0.922ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.718     3.924    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X96Y240        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y240        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     3.963 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_14/Q
                         net (fo=188, routed)         0.232     4.195    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_14_alias
    SLICE_X85Y229        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.878     3.849    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X85Y229        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.137     3.986    
    SLICE_X85Y229        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.966    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.966    
                         arrival time                           4.195    
  -------------------------------------------------------------------
                         slack                                  0.229    

Slack (MET) :             0.413ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.457ns  (logic 0.039ns (8.539%)  route 0.418ns (91.461%))
  Logic Levels:           0  
  Clock Path Skew:        0.064ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.783ns
    Source Clock Delay      (SCD):    3.812ns
    Clock Pessimism Removal (CPR):    -0.092ns
  Clock Net Delay (Source):      1.606ns (routing 0.858ns, distribution 0.748ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.956ns, distribution 0.856ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.606     3.812    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X67Y199        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y199        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.851 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                         net (fo=260, routed)         0.418     4.268    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/peripheral_aresetn[0]_repN_2_alias
    SLICE_X79Y217        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.812     3.783    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X79Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.092     3.875    
    SLICE_X79Y217        FDCE (Remov_AFF_SLICEM_C_CLR)
                                                     -0.020     3.855    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.855    
                         arrival time                           4.268    
  -------------------------------------------------------------------
                         slack                                  0.413    

Slack (MET) :             0.413ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.457ns  (logic 0.039ns (8.539%)  route 0.418ns (91.461%))
  Logic Levels:           0  
  Clock Path Skew:        0.064ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.783ns
    Source Clock Delay      (SCD):    3.812ns
    Clock Pessimism Removal (CPR):    -0.092ns
  Clock Net Delay (Source):      1.606ns (routing 0.858ns, distribution 0.748ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.956ns, distribution 0.856ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.606     3.812    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X67Y199        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y199        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.851 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_2/Q
                         net (fo=260, routed)         0.418     4.268    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_2_alias
    SLICE_X79Y217        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.812     3.783    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X79Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.092     3.875    
    SLICE_X79Y217        FDCE (Remov_AFF2_SLICEM_C_CLR)
                                                     -0.020     3.855    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.855    
                         arrival time                           4.268    
  -------------------------------------------------------------------
                         slack                                  0.413    

Slack (MET) :             0.511ns  (arrival time - required time)
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_7/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns - clk_out1_d_1_clk_adc0_x2_0 rise@0.000ns)
  Data Path Delay:        0.481ns  (logic 0.038ns (7.898%)  route 0.443ns (92.102%))
  Logic Levels:           0  
  Clock Path Skew:        -0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.843ns
    Source Clock Delay      (SCD):    3.938ns
    Clock Pessimism Removal (CPR):    -0.085ns
  Clock Net Delay (Source):      1.732ns (routing 0.858ns, distribution 0.874ns)
  Clock Net Delay (Destination): 1.872ns (routing 0.956ns, distribution 0.916ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.732     3.938    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X97Y225        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_7/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y225        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.976 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_7/Q
                         net (fo=109, routed)         0.443     4.419    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/peripheral_aresetn[0]_repN_7_alias
    SLICE_X85Y217        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.872     3.843    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X85Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]/C
                         clock pessimism              0.085     3.928    
    SLICE_X85Y217        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.908    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -3.908    
                         arrival time                           4.419    
  -------------------------------------------------------------------
                         slack                                  0.511    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        0.739ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.099ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.739ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[11][8]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.037ns  (logic 0.079ns (1.957%)  route 3.958ns (98.043%))
  Logic Levels:           0  
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.400ns = ( 10.400 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.262ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.327ns (routing 1.464ns, distribution 0.863ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.958     9.271    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_3_alias
    SLICE_X34Y207        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[11][8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.327    10.400    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X34Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[11][8]/C
                         clock pessimism             -0.262    10.138    
                         clock uncertainty           -0.062    10.076    
    SLICE_X34Y207        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    10.010    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[11][8]
  -------------------------------------------------------------------
                         required time                         10.010    
                         arrival time                          -9.271    
  -------------------------------------------------------------------
                         slack                                  0.739    

Slack (MET) :             1.023ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.729ns  (logic 0.079ns (2.119%)  route 3.650ns (97.881%))
  Logic Levels:           0  
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.376ns = ( 10.376 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.261ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.303ns (routing 1.464ns, distribution 0.839ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.650     8.963    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_3_alias
    SLICE_X22Y213        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.303    10.376    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X22Y213        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[0]/C
                         clock pessimism             -0.261    10.114    
                         clock uncertainty           -0.062    10.052    
    SLICE_X22Y213        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     9.986    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[0]
  -------------------------------------------------------------------
                         required time                          9.986    
                         arrival time                          -8.963    
  -------------------------------------------------------------------
                         slack                                  1.023    

Slack (MET) :             1.106ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[18]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.741ns  (logic 0.079ns (2.112%)  route 3.662ns (97.888%))
  Logic Levels:           0  
  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.469ns = ( 10.469 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.396ns (routing 1.464ns, distribution 0.932ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.662     8.975    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_3_alias
    SLICE_X15Y220        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[18]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.396    10.469    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X15Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[18]/C
                         clock pessimism             -0.259    10.209    
                         clock uncertainty           -0.062    10.147    
    SLICE_X15Y220        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066    10.081    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[18]
  -------------------------------------------------------------------
                         required time                         10.081    
                         arrival time                          -8.975    
  -------------------------------------------------------------------
                         slack                                  1.106    

Slack (MET) :             1.106ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[19]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.741ns  (logic 0.079ns (2.112%)  route 3.662ns (97.888%))
  Logic Levels:           0  
  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.469ns = ( 10.469 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.396ns (routing 1.464ns, distribution 0.932ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.662     8.975    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_3_alias
    SLICE_X15Y220        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[19]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.396    10.469    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X15Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[19]/C
                         clock pessimism             -0.259    10.209    
                         clock uncertainty           -0.062    10.147    
    SLICE_X15Y220        FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                     -0.066    10.081    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[19]
  -------------------------------------------------------------------
                         required time                         10.081    
                         arrival time                          -8.975    
  -------------------------------------------------------------------
                         slack                                  1.106    

Slack (MET) :             1.106ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[20]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.741ns  (logic 0.079ns (2.112%)  route 3.662ns (97.888%))
  Logic Levels:           0  
  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.469ns = ( 10.469 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.396ns (routing 1.464ns, distribution 0.932ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.662     8.975    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_3_alias
    SLICE_X15Y220        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[20]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.396    10.469    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X15Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[20]/C
                         clock pessimism             -0.259    10.209    
                         clock uncertainty           -0.062    10.147    
    SLICE_X15Y220        FDCE (Recov_FFF_SLICEL_C_CLR)
                                                     -0.066    10.081    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[20]
  -------------------------------------------------------------------
                         required time                         10.081    
                         arrival time                          -8.975    
  -------------------------------------------------------------------
                         slack                                  1.106    

Slack (MET) :             1.106ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[21]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.741ns  (logic 0.079ns (2.112%)  route 3.662ns (97.888%))
  Logic Levels:           0  
  Clock Path Skew:        -0.025ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.469ns = ( 10.469 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.396ns (routing 1.464ns, distribution 0.932ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.662     8.975    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_3_alias
    SLICE_X15Y220        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[21]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.396    10.469    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X15Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[21]/C
                         clock pessimism             -0.259    10.209    
                         clock uncertainty           -0.062    10.147    
    SLICE_X15Y220        FDCE (Recov_FFF2_SLICEL_C_CLR)
                                                     -0.066    10.081    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[21]
  -------------------------------------------------------------------
                         required time                         10.081    
                         arrival time                          -8.975    
  -------------------------------------------------------------------
                         slack                                  1.106    

Slack (MET) :             1.119ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[4][12]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.638ns  (logic 0.079ns (2.172%)  route 3.559ns (97.828%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.381ns = ( 10.381 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.261ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.308ns (routing 1.464ns, distribution 0.844ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.559     8.872    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_3_alias
    SLICE_X29Y210        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[4][12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.308    10.381    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X29Y210        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[4][12]/C
                         clock pessimism             -0.261    10.119    
                         clock uncertainty           -0.062    10.057    
    SLICE_X29Y210        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066     9.991    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/dreg_32_dt_reg[4][12]
  -------------------------------------------------------------------
                         required time                          9.991    
                         arrival time                          -8.872    
  -------------------------------------------------------------------
                         slack                                  1.119    

Slack (MET) :             1.152ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[13]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.698ns  (logic 0.079ns (2.136%)  route 3.619ns (97.864%))
  Logic Levels:           0  
  Clock Path Skew:        -0.022ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.472ns = ( 10.472 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.399ns (routing 1.464ns, distribution 0.935ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.619     8.932    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_3_alias
    SLICE_X13Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.399    10.472    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X13Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[13]/C
                         clock pessimism             -0.259    10.212    
                         clock uncertainty           -0.062    10.150    
    SLICE_X13Y212        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    10.084    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[13]
  -------------------------------------------------------------------
                         required time                         10.084    
                         arrival time                          -8.932    
  -------------------------------------------------------------------
                         slack                                  1.152    

Slack (MET) :             1.152ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[29]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.698ns  (logic 0.079ns (2.136%)  route 3.619ns (97.864%))
  Logic Levels:           0  
  Clock Path Skew:        -0.022ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.472ns = ( 10.472 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.399ns (routing 1.464ns, distribution 0.935ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.619     8.932    d_1_i/qick_processor_0/inst/QPROC/peripheral_aresetn[0]_repN_3_alias
    SLICE_X13Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[29]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.399    10.472    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X13Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[29]/C
                         clock pessimism             -0.259    10.212    
                         clock uncertainty           -0.062    10.150    
    SLICE_X13Y212        FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                     -0.066    10.084    d_1_i/qick_processor_0/inst/QPROC/QPER_DIV.div_remainder_r_reg[29]
  -------------------------------------------------------------------
                         required time                         10.084    
                         arrival time                          -8.932    
  -------------------------------------------------------------------
                         slack                                  1.152    

Slack (MET) :             1.164ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[2][26]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        3.685ns  (logic 0.079ns (2.144%)  route 3.606ns (97.856%))
  Logic Levels:           0  
  Clock Path Skew:        -0.023ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.471ns = ( 10.471 - 5.000 ) 
    Source Clock Delay      (SCD):    5.234ns
    Clock Pessimism Removal (CPR):    -0.259ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.619ns (routing 1.611ns, distribution 1.008ns)
  Clock Net Delay (Destination): 2.398ns (routing 1.464ns, distribution 0.934ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.619     5.234    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X32Y225        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y225        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.313 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_3/Q
                         net (fo=247, routed)         3.606     8.919    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/peripheral_aresetn[0]_repN_3_alias
    SLICE_X14Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[2][26]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     7.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     8.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     8.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.398    10.471    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X14Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[2][26]/C
                         clock pessimism             -0.259    10.211    
                         clock uncertainty           -0.062    10.149    
    SLICE_X14Y212        FDCE (Recov_HFF2_SLICEL_C_CLR)
                                                     -0.066    10.083    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/sreg_dt_reg[2][26]
  -------------------------------------------------------------------
                         required time                         10.083    
                         arrival time                          -8.919    
  -------------------------------------------------------------------
                         slack                                  1.164    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.099ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.109ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.978ns, distribution 0.724ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X58Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.702     3.109    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                         clock pessimism              0.198     3.307    
    SLICE_X58Y232        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.287    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]
  -------------------------------------------------------------------
                         required time                         -3.287    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.099    

Slack (MET) :             0.099ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.109ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.978ns, distribution 0.724ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X59Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.702     3.109    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]/C
                         clock pessimism              0.198     3.307    
    SLICE_X59Y232        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.287    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.287    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.099    

Slack (MET) :             0.099ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.109ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.978ns, distribution 0.724ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X58Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.702     3.109    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/C
                         clock pessimism              0.198     3.307    
    SLICE_X58Y232        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     3.287    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]
  -------------------------------------------------------------------
                         required time                         -3.287    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.099    

Slack (MET) :             0.099ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.109ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.978ns, distribution 0.724ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X58Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.702     3.109    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/C
                         clock pessimism              0.198     3.307    
    SLICE_X58Y232        FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     3.287    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]
  -------------------------------------------------------------------
                         required time                         -3.287    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.099    

Slack (MET) :             0.099ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.109ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.702ns (routing 0.978ns, distribution 0.724ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X58Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.702     3.109    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/C
                         clock pessimism              0.198     3.307    
    SLICE_X58Y232        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     3.287    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.287    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.099    

Slack (MET) :             0.103ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.105ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.698ns (routing 0.978ns, distribution 0.720ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X58Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.698     3.105    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                         clock pessimism              0.198     3.303    
    SLICE_X58Y232        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     3.283    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]
  -------------------------------------------------------------------
                         required time                         -3.283    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.103    

Slack (MET) :             0.103ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.105ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.698ns (routing 0.978ns, distribution 0.720ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X58Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.698     3.105    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                         clock pessimism              0.198     3.303    
    SLICE_X58Y232        FDCE (Remov_CFF_SLICEL_C_CLR)
                                                     -0.020     3.283    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.283    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.103    

Slack (MET) :             0.103ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.105ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.698ns (routing 0.978ns, distribution 0.720ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X58Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.698     3.105    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/C
                         clock pessimism              0.198     3.303    
    SLICE_X58Y232        FDCE (Remov_BFF_SLICEL_C_CLR)
                                                     -0.020     3.283    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]
  -------------------------------------------------------------------
                         required time                         -3.283    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.103    

Slack (MET) :             0.103ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.789%)  route 0.101ns (72.211%))
  Logic Levels:           0  
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.105ns
    Source Clock Delay      (SCD):    3.246ns
    Clock Pessimism Removal (CPR):    -0.198ns
  Clock Net Delay (Source):      1.506ns (routing 0.877ns, distribution 0.629ns)
  Clock Net Delay (Destination): 1.698ns (routing 0.978ns, distribution 0.720ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.506     3.246    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y232        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y232        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.285 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_12/Q
                         net (fo=203, routed)         0.101     3.386    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_12_alias
    SLICE_X58Y232        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.698     3.105    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                         clock pessimism              0.198     3.303    
    SLICE_X58Y232        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     3.283    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                         -3.283    
                         arrival time                           3.386    
  -------------------------------------------------------------------
                         slack                                  0.103    

Slack (MET) :             0.117ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_9/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.112ns  (logic 0.039ns (34.920%)  route 0.073ns (65.080%))
  Logic Levels:           0  
  Clock Path Skew:        0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.101ns
    Source Clock Delay      (SCD):    3.247ns
    Clock Pessimism Removal (CPR):    -0.160ns
  Clock Net Delay (Source):      1.507ns (routing 0.877ns, distribution 0.630ns)
  Clock Net Delay (Destination): 1.694ns (routing 0.978ns, distribution 0.716ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.507     3.247    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X58Y209        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_9/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y209        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.286 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica_9/Q
                         net (fo=78, routed)          0.073     3.358    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/peripheral_aresetn[0]_repN_9_alias
    SLICE_X59Y209        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.694     3.101    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y209        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                         clock pessimism              0.160     3.261    
    SLICE_X59Y209        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     3.241    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]
  -------------------------------------------------------------------
                         required time                         -3.241    
                         arrival time                           3.358    
  -------------------------------------------------------------------
                         slack                                  0.117    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        6.678ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.159ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.678ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DR_START_REG_resync_i/data_int_reg_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.746ns  (logic 0.104ns (3.787%)  route 2.642ns (96.213%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.380ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.105ns = ( 12.105 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.923ns (routing 0.703ns, distribution 1.220ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.617     5.353    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DR_START_REG_resync_i/SR[0]
    SLICE_X55Y118        FDCE                                         f  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DR_START_REG_resync_i/data_int_reg_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.923    12.105    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DR_START_REG_resync_i/m00_axis_aclk
    SLICE_X55Y118        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DR_START_REG_resync_i/data_int_reg_reg[0]/C
                         clock pessimism              0.122    12.227    
                         clock uncertainty           -0.130    12.097    
    SLICE_X55Y118        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066    12.031    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DR_START_REG_resync_i/data_int_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.031    
                         arrival time                          -5.353    
  -------------------------------------------------------------------
                         slack                                  6.678    

Slack (MET) :             6.946ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][6]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.575ns  (logic 0.104ns (4.039%)  route 2.471ns (95.961%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.283ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.128ns = ( 12.128 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.703ns, distribution 1.243ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.446     5.182    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X39Y202        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.946    12.128    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X39Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][6]/C
                         clock pessimism              0.197    12.324    
                         clock uncertainty           -0.130    12.194    
    SLICE_X39Y202        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.128    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][6]
  -------------------------------------------------------------------
                         required time                         12.129    
                         arrival time                          -5.182    
  -------------------------------------------------------------------
                         slack                                  6.946    

Slack (MET) :             6.946ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][3]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.575ns  (logic 0.104ns (4.039%)  route 2.471ns (95.961%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.283ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.128ns = ( 12.128 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.946ns (routing 0.703ns, distribution 1.243ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.446     5.182    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X39Y202        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.946    12.128    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X39Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][3]/C
                         clock pessimism              0.197    12.324    
                         clock uncertainty           -0.130    12.194    
    SLICE_X39Y202        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    12.128    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][3]
  -------------------------------------------------------------------
                         required time                         12.129    
                         arrival time                          -5.182    
  -------------------------------------------------------------------
                         slack                                  6.946    

Slack (MET) :             6.948ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.733ns  (logic 0.104ns (3.805%)  route 2.629ns (96.195%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.123ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns = ( 12.285 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.199ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 2.103ns (routing 0.703ns, distribution 1.400ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.604     5.340    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X18Y201        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.103    12.285    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X18Y201        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]/C
                         clock pessimism              0.199    12.484    
                         clock uncertainty           -0.130    12.354    
    SLICE_X18Y201        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.288    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][25]
  -------------------------------------------------------------------
                         required time                         12.288    
                         arrival time                          -5.340    
  -------------------------------------------------------------------
                         slack                                  6.948    

Slack (MET) :             6.948ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.733ns  (logic 0.104ns (3.805%)  route 2.629ns (96.195%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.123ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns = ( 12.285 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.199ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 2.103ns (routing 0.703ns, distribution 1.400ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.604     5.340    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X18Y201        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.103    12.285    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X18Y201        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]/C
                         clock pessimism              0.199    12.484    
                         clock uncertainty           -0.130    12.354    
    SLICE_X18Y201        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    12.288    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][27]
  -------------------------------------------------------------------
                         required time                         12.288    
                         arrival time                          -5.340    
  -------------------------------------------------------------------
                         slack                                  6.948    

Slack (MET) :             6.950ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][28]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.649ns  (logic 0.104ns (3.926%)  route 2.545ns (96.074%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.205ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.203ns = ( 12.203 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.199ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 2.021ns (routing 0.703ns, distribution 1.318ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.520     5.256    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X21Y203        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][28]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.021    12.203    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X21Y203        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][28]/C
                         clock pessimism              0.199    12.402    
                         clock uncertainty           -0.130    12.272    
    SLICE_X21Y203        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.206    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][28]
  -------------------------------------------------------------------
                         required time                         12.206    
                         arrival time                          -5.256    
  -------------------------------------------------------------------
                         slack                                  6.950    

Slack (MET) :             6.952ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][13]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.559ns  (logic 0.104ns (4.064%)  route 2.455ns (95.936%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.117ns = ( 12.117 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.935ns (routing 0.703ns, distribution 1.232ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.430     5.166    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X42Y202        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.935    12.117    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X42Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][13]/C
                         clock pessimism              0.197    12.314    
                         clock uncertainty           -0.130    12.184    
    SLICE_X42Y202        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.118    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[1][13]
  -------------------------------------------------------------------
                         required time                         12.118    
                         arrival time                          -5.166    
  -------------------------------------------------------------------
                         slack                                  6.952    

Slack (MET) :             6.953ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][8]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.562ns  (logic 0.104ns (4.059%)  route 2.458ns (95.941%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.289ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.121ns = ( 12.121 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.939ns (routing 0.703ns, distribution 1.236ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.433     5.169    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X41Y202        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.939    12.121    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X41Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][8]/C
                         clock pessimism              0.197    12.318    
                         clock uncertainty           -0.130    12.188    
    SLICE_X41Y202        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.122    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][8]
  -------------------------------------------------------------------
                         required time                         12.122    
                         arrival time                          -5.169    
  -------------------------------------------------------------------
                         slack                                  6.953    

Slack (MET) :             6.953ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][19]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.623ns  (logic 0.104ns (3.965%)  route 2.519ns (96.035%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.228ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.180ns = ( 12.180 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.199ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.998ns (routing 0.703ns, distribution 1.295ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.494     5.230    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X27Y213        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][19]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.998    12.180    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X27Y213        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][19]/C
                         clock pessimism              0.199    12.379    
                         clock uncertainty           -0.130    12.249    
    SLICE_X27Y213        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.183    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][19]
  -------------------------------------------------------------------
                         required time                         12.183    
                         arrival time                          -5.230    
  -------------------------------------------------------------------
                         slack                                  6.953    

Slack (MET) :             6.954ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][31]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.718ns  (logic 0.104ns (3.826%)  route 2.614ns (96.174%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.132ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.276ns = ( 12.276 - 10.000 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.199ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.381ns (routing 0.777ns, distribution 1.604ns)
  Clock Net Delay (Destination): 2.094ns (routing 0.703ns, distribution 1.391ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.381     2.607    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X89Y225        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y225        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.683 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.025     3.708    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y104        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.736 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=12448, routed)       1.589     5.325    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X18Y204        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][31]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.094    12.276    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X18Y204        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][31]/C
                         clock pessimism              0.199    12.475    
                         clock uncertainty           -0.130    12.345    
    SLICE_X18Y204        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    12.279    d_1_i/qick_processor_0/inst/QPROC/xreg_TPROC_R_DT_reg[0][31]
  -------------------------------------------------------------------
                         required time                         12.279    
                         arrival time                          -5.325    
  -------------------------------------------------------------------
                         slack                                  6.954    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.159ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.060ns (31.988%)  route 0.128ns (68.012%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.546ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.243ns (routing 0.421ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.399ns (routing 0.472ns, distribution 0.927ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.243     1.363    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y161        FDRE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y161        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.401 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.429    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y161        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.022     1.451 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.099     1.550    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X26Y161        FDCE                                         f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.399     1.546    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X26Y161        FDCE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]/C
                         clock pessimism             -0.135     1.411    
    SLICE_X26Y161        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     1.391    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.391    
                         arrival time                           1.550    
  -------------------------------------------------------------------
                         slack                                  0.159    

Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.060ns (31.988%)  route 0.128ns (68.012%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.542ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.243ns (routing 0.421ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.395ns (routing 0.472ns, distribution 0.923ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.243     1.363    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y161        FDRE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y161        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.401 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.429    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y161        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.022     1.451 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.099     1.550    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X26Y161        FDPE                                         f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.395     1.542    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X26Y161        FDPE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]/C
                         clock pessimism             -0.135     1.407    
    SLICE_X26Y161        FDPE (Remov_BFF2_SLICEL_C_PRE)
                                                     -0.020     1.387    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.387    
                         arrival time                           1.550    
  -------------------------------------------------------------------
                         slack                                  0.163    

Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.060ns (31.988%)  route 0.128ns (68.012%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.542ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.243ns (routing 0.421ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.395ns (routing 0.472ns, distribution 0.923ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.243     1.363    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y161        FDRE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y161        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.401 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.429    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y161        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.022     1.451 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.099     1.550    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X26Y161        FDCE                                         f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.395     1.542    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X26Y161        FDCE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C
                         clock pessimism             -0.135     1.407    
    SLICE_X26Y161        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     1.387    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.387    
                         arrival time                           1.550    
  -------------------------------------------------------------------
                         slack                                  0.163    

Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.060ns (31.988%)  route 0.128ns (68.012%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.542ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.243ns (routing 0.421ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.395ns (routing 0.472ns, distribution 0.923ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.243     1.363    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y161        FDRE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y161        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.401 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.429    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y161        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.022     1.451 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.099     1.550    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X26Y161        FDCE                                         f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.395     1.542    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X26Y161        FDCE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C
                         clock pessimism             -0.135     1.407    
    SLICE_X26Y161        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     1.387    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.387    
                         arrival time                           1.550    
  -------------------------------------------------------------------
                         slack                                  0.163    

Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.060ns (31.988%)  route 0.128ns (68.012%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.542ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.243ns (routing 0.421ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.395ns (routing 0.472ns, distribution 0.923ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.243     1.363    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y161        FDRE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y161        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.401 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.429    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y161        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.022     1.451 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.099     1.550    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X26Y161        FDCE                                         f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.395     1.542    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X26Y161        FDCE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C
                         clock pessimism             -0.135     1.407    
    SLICE_X26Y161        FDCE (Remov_CFF_SLICEL_C_CLR)
                                                     -0.020     1.387    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.387    
                         arrival time                           1.550    
  -------------------------------------------------------------------
                         slack                                  0.163    

Slack (MET) :             0.163ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.060ns (31.988%)  route 0.128ns (68.012%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.542ns
    Source Clock Delay      (SCD):    1.363ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.243ns (routing 0.421ns, distribution 0.822ns)
  Clock Net Delay (Destination): 1.395ns (routing 0.472ns, distribution 0.923ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.243     1.363    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y161        FDRE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y161        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.401 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.029     1.429    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y161        LUT3 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.022     1.451 f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.099     1.550    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X26Y161        FDCE                                         f  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.395     1.542    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X26Y161        FDCE                                         r  d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4]/C
                         clock pessimism             -0.135     1.407    
    SLICE_X26Y161        FDCE (Remov_CFF2_SLICEL_C_CLR)
                                                     -0.020     1.387    d_1_i/ps8_0_axi_periph/m02_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.387    
                         arrival time                           1.550    
  -------------------------------------------------------------------
                         slack                                  0.163    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.061ns (31.057%)  route 0.135ns (68.943%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.547ns
    Source Clock Delay      (SCD):    1.362ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.242ns (routing 0.421ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.472ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.242     1.362    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X33Y126        FDRE                                         r  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y126        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.401 f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.426    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X33Y126        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.448 f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.110     1.558    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X34Y126        FDCE                                         f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.400     1.547    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X34Y126        FDCE                                         r  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]/C
                         clock pessimism             -0.135     1.412    
    SLICE_X34Y126        FDCE (Remov_CFF_SLICEM_C_CLR)
                                                     -0.020     1.392    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           1.558    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.061ns (31.057%)  route 0.135ns (68.943%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.547ns
    Source Clock Delay      (SCD):    1.362ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.242ns (routing 0.421ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.472ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.242     1.362    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X33Y126        FDRE                                         r  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y126        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.401 f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.426    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X33Y126        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.448 f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.110     1.558    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X34Y126        FDCE                                         f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.400     1.547    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X34Y126        FDCE                                         r  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]/C
                         clock pessimism             -0.135     1.412    
    SLICE_X34Y126        FDCE (Remov_CFF2_SLICEM_C_CLR)
                                                     -0.020     1.392    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           1.558    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.061ns (31.057%)  route 0.135ns (68.943%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.547ns
    Source Clock Delay      (SCD):    1.362ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.242ns (routing 0.421ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.472ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.242     1.362    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X33Y126        FDRE                                         r  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y126        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.401 f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.426    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X33Y126        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.448 f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.110     1.558    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X34Y126        FDCE                                         f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.400     1.547    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X34Y126        FDCE                                         r  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]/C
                         clock pessimism             -0.135     1.412    
    SLICE_X34Y126        FDCE (Remov_BFF_SLICEM_C_CLR)
                                                     -0.020     1.392    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           1.558    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.061ns (31.057%)  route 0.135ns (68.943%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.547ns
    Source Clock Delay      (SCD):    1.362ns
    Clock Pessimism Removal (CPR):    0.135ns
  Clock Net Delay (Source):      1.242ns (routing 0.421ns, distribution 0.821ns)
  Clock Net Delay (Destination): 1.400ns (routing 0.472ns, distribution 0.928ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.242     1.362    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X33Y126        FDRE                                         r  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y126        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.401 f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[1]/Q
                         net (fo=2, routed)           0.026     1.426    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[1]
    SLICE_X33Y126        LUT3 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.448 f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.110     1.558    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_d1_reg[4]_1
    SLICE_X34Y126        FDCE                                         f  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.400     1.547    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/clk
    SLICE_X34Y126        FDCE                                         r  d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4]/C
                         clock pessimism             -0.135     1.412    
    SLICE_X34Y126        FDCE (Remov_BFF2_SLICEM_C_CLR)
                                                     -0.020     1.392    d_1_i/ps8_0_axi_periph/m07_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/gc0.count_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.392    
                         arrival time                           1.558    
  -------------------------------------------------------------------
                         slack                                  0.166    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       47.003ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.104ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             47.003ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.740ns  (logic 0.316ns (11.533%)  route 2.424ns (88.467%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.195    10.242    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y332       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
                         clock pessimism              4.314    57.346    
                         clock uncertainty           -0.035    57.310    
    SLICE_X101Y332       FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066    57.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]
  -------------------------------------------------------------------
                         required time                         57.244    
                         arrival time                         -10.242    
  -------------------------------------------------------------------
                         slack                                 47.003    

Slack (MET) :             47.003ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.740ns  (logic 0.316ns (11.533%)  route 2.424ns (88.467%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.195    10.242    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y332       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              4.314    57.346    
                         clock uncertainty           -0.035    57.310    
    SLICE_X101Y332       FDCE (Recov_AFF2_SLICEL_C_CLR)
                                                     -0.066    57.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                         57.244    
                         arrival time                         -10.242    
  -------------------------------------------------------------------
                         slack                                 47.003    

Slack (MET) :             47.003ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.740ns  (logic 0.316ns (11.533%)  route 2.424ns (88.467%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.195    10.242    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y332       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/C
                         clock pessimism              4.314    57.346    
                         clock uncertainty           -0.035    57.310    
    SLICE_X101Y332       FDCE (Recov_BFF_SLICEL_C_CLR)
                                                     -0.066    57.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]
  -------------------------------------------------------------------
                         required time                         57.244    
                         arrival time                         -10.242    
  -------------------------------------------------------------------
                         slack                                 47.003    

Slack (MET) :             47.003ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.740ns  (logic 0.316ns (11.533%)  route 2.424ns (88.467%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.195    10.242    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y332       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
                         clock pessimism              4.314    57.346    
                         clock uncertainty           -0.035    57.310    
    SLICE_X101Y332       FDCE (Recov_BFF2_SLICEL_C_CLR)
                                                     -0.066    57.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]
  -------------------------------------------------------------------
                         required time                         57.244    
                         arrival time                         -10.242    
  -------------------------------------------------------------------
                         slack                                 47.003    

Slack (MET) :             47.003ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.740ns  (logic 0.316ns (11.533%)  route 2.424ns (88.467%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.195    10.242    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y332       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/C
                         clock pessimism              4.314    57.346    
                         clock uncertainty           -0.035    57.310    
    SLICE_X101Y332       FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    57.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]
  -------------------------------------------------------------------
                         required time                         57.244    
                         arrival time                         -10.242    
  -------------------------------------------------------------------
                         slack                                 47.003    

Slack (MET) :             47.003ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.740ns  (logic 0.316ns (11.533%)  route 2.424ns (88.467%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.195    10.242    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y332       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              4.314    57.346    
                         clock uncertainty           -0.035    57.310    
    SLICE_X101Y332       FDCE (Recov_CFF2_SLICEL_C_CLR)
                                                     -0.066    57.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         57.244    
                         arrival time                         -10.242    
  -------------------------------------------------------------------
                         slack                                 47.003    

Slack (MET) :             47.003ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.740ns  (logic 0.316ns (11.533%)  route 2.424ns (88.467%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.156ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.032ns = ( 53.032 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.631ns (routing 0.483ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.195    10.242    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y332       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.631    53.032    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y332       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
                         clock pessimism              4.314    57.346    
                         clock uncertainty           -0.035    57.310    
    SLICE_X101Y332       FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    57.244    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]
  -------------------------------------------------------------------
                         required time                         57.244    
                         arrival time                         -10.242    
  -------------------------------------------------------------------
                         slack                                 47.003    

Slack (MET) :             47.046ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.693ns  (logic 0.316ns (11.735%)  route 2.377ns (88.265%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.160ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.028ns = ( 53.028 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.627ns (routing 0.483ns, distribution 1.144ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.148    10.195    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y331       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.627    53.028    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y331       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/C
                         clock pessimism              4.314    57.342    
                         clock uncertainty           -0.035    57.307    
    SLICE_X101Y331       FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066    57.241    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]
  -------------------------------------------------------------------
                         required time                         57.241    
                         arrival time                         -10.195    
  -------------------------------------------------------------------
                         slack                                 47.046    

Slack (MET) :             47.046ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.693ns  (logic 0.316ns (11.735%)  route 2.377ns (88.265%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.160ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.028ns = ( 53.028 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.627ns (routing 0.483ns, distribution 1.144ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.148    10.195    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y331       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.627    53.028    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y331       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism              4.314    57.342    
                         clock uncertainty           -0.035    57.307    
    SLICE_X101Y331       FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                     -0.066    57.241    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         57.241    
                         arrival time                         -10.195    
  -------------------------------------------------------------------
                         slack                                 47.046    

Slack (MET) :             47.046ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.693ns  (logic 0.316ns (11.735%)  route 2.377ns (88.265%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.160ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.028ns = ( 53.028 - 50.000 ) 
    Source Clock Delay      (SCD):    7.502ns
    Clock Pessimism Removal (CPR):    4.314ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.837ns (routing 0.533ns, distribution 1.304ns)
  Clock Net Delay (Destination): 1.627ns (routing 0.483ns, distribution 1.144ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.837     7.502    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y90        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y90        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.583 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.145     7.728    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X100Y90        LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     7.852 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.084     7.936    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X99Y91         LUT4 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.111     8.047 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          2.148    10.195    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X101Y331       FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912    51.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.627    53.028    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X101Y331       FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/C
                         clock pessimism              4.314    57.342    
                         clock uncertainty           -0.035    57.307    
    SLICE_X101Y331       FDCE (Recov_FFF_SLICEL_C_CLR)
                                                     -0.066    57.241    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]
  -------------------------------------------------------------------
                         required time                         57.241    
                         arrival time                         -10.195    
  -------------------------------------------------------------------
                         slack                                 47.046    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.040ns (28.488%)  route 0.100ns (71.512%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.100     2.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X88Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/C
                         clock pessimism             -4.149     2.247    
    SLICE_X88Y362        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     2.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.227    
                         arrival time                           2.332    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.040ns (28.488%)  route 0.100ns (71.512%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.100     2.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X88Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/C
                         clock pessimism             -4.149     2.247    
    SLICE_X88Y362        FDCE (Remov_GFF2_SLICEL_C_CLR)
                                                     -0.020     2.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.227    
                         arrival time                           2.332    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.040ns (28.488%)  route 0.100ns (71.512%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.100     2.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X88Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/C
                         clock pessimism             -4.149     2.247    
    SLICE_X88Y362        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     2.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.227    
                         arrival time                           2.332    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.040ns (28.488%)  route 0.100ns (71.512%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.100     2.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X88Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[3]/C
                         clock pessimism             -4.149     2.247    
    SLICE_X88Y362        FDCE (Remov_FFF2_SLICEL_C_CLR)
                                                     -0.020     2.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.227    
                         arrival time                           2.332    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.040ns (28.488%)  route 0.100ns (71.512%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.100     2.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
    SLICE_X88Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                         clock pessimism             -4.149     2.247    
    SLICE_X88Y362        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     2.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.227    
                         arrival time                           2.332    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.040ns (28.488%)  route 0.100ns (71.512%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.100     2.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
    SLICE_X88Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                         clock pessimism             -4.149     2.247    
    SLICE_X88Y362        FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     2.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.227    
                         arrival time                           2.332    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.104ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.040ns (28.488%)  route 0.100ns (71.512%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.100     2.332    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
    SLICE_X88Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                         clock pessimism             -4.149     2.247    
    SLICE_X88Y362        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     2.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.227    
                         arrival time                           2.332    
  -------------------------------------------------------------------
                         slack                                  0.104    

Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.147ns  (logic 0.040ns (27.136%)  route 0.107ns (72.864%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.400ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.140ns (routing 0.330ns, distribution 0.810ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.107     2.339    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X87Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.140     6.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X87Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C
                         clock pessimism             -4.149     2.251    
    SLICE_X87Y362        FDCE (Remov_DFF2_SLICEM_C_CLR)
                                                     -0.020     2.231    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.231    
                         arrival time                           2.339    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.147ns  (logic 0.040ns (27.136%)  route 0.107ns (72.864%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.400ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.140ns (routing 0.330ns, distribution 0.810ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.107     2.339    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X87Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.140     6.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
    SLICE_X87Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/C
                         clock pessimism             -4.149     2.251    
    SLICE_X87Y362        FDCE (Remov_AFF2_SLICEM_C_CLR)
                                                     -0.020     2.231    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.231    
                         arrival time                           2.339    
  -------------------------------------------------------------------
                         slack                                  0.107    

Slack (MET) :             0.107ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.147ns  (logic 0.040ns (27.136%)  route 0.107ns (72.864%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.400ns
    Source Clock Delay      (SCD):    2.192ns
    Clock Pessimism Removal (CPR):    4.149ns
  Clock Net Delay (Source):      0.999ns (routing 0.294ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.140ns (routing 0.330ns, distribution 0.810ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         0.999     2.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X85Y362        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y362        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.232 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.107     2.339    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
    SLICE_X87Y362        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.140     6.400    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X87Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/C
                         clock pessimism             -4.149     2.251    
    SLICE_X87Y362        FDCE (Remov_CFF_SLICEM_C_CLR)
                                                     -0.020     2.231    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.231    
                         arrival time                           2.339    
  -------------------------------------------------------------------
                         slack                                  0.107    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       10.337ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.116ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             10.337ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.404ns  (logic 0.076ns (5.413%)  route 1.328ns (94.587%))
  Logic Levels:           0  
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.956ns = ( 15.958 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.330ns (routing 0.578ns, distribution 0.752ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.328     5.097    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X91Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.330    15.958    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X91Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/C
                         clock pessimism             -0.382    15.576    
                         clock uncertainty           -0.076    15.500    
    SLICE_X91Y371        FDCE (Recov_HFF2_SLICEL_C_CLR)
                                                     -0.066    15.434    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg
  -------------------------------------------------------------------
                         required time                         15.434    
                         arrival time                          -5.097    
  -------------------------------------------------------------------
                         slack                                 10.337    

Slack (MET) :             10.337ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.404ns  (logic 0.076ns (5.413%)  route 1.328ns (94.587%))
  Logic Levels:           0  
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.956ns = ( 15.958 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.330ns (routing 0.578ns, distribution 0.752ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.328     5.097    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X91Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.330    15.958    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X91Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[0]/C
                         clock pessimism             -0.382    15.576    
                         clock uncertainty           -0.076    15.500    
    SLICE_X91Y371        FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066    15.434    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[0]
  -------------------------------------------------------------------
                         required time                         15.434    
                         arrival time                          -5.097    
  -------------------------------------------------------------------
                         slack                                 10.337    

Slack (MET) :             10.337ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.404ns  (logic 0.076ns (5.413%)  route 1.328ns (94.587%))
  Logic Levels:           0  
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.956ns = ( 15.958 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.330ns (routing 0.578ns, distribution 0.752ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.328     5.097    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X91Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.330    15.958    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X91Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/C
                         clock pessimism             -0.382    15.576    
                         clock uncertainty           -0.076    15.500    
    SLICE_X91Y371        FDCE (Recov_GFF_SLICEL_C_CLR)
                                                     -0.066    15.434    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]
  -------------------------------------------------------------------
                         required time                         15.434    
                         arrival time                          -5.097    
  -------------------------------------------------------------------
                         slack                                 10.337    

Slack (MET) :             10.468ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.289ns  (logic 0.076ns (5.897%)  route 1.213ns (94.102%))
  Logic Levels:           0  
  Clock Path Skew:        -0.104ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.971ns = ( 15.974 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.345ns (routing 0.578ns, distribution 0.767ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.213     4.982    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X87Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.345    15.974    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X87Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/C
                         clock pessimism             -0.382    15.591    
                         clock uncertainty           -0.076    15.516    
    SLICE_X87Y371        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    15.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]
  -------------------------------------------------------------------
                         required time                         15.450    
                         arrival time                          -4.982    
  -------------------------------------------------------------------
                         slack                                 10.468    

Slack (MET) :             10.468ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.289ns  (logic 0.076ns (5.897%)  route 1.213ns (94.102%))
  Logic Levels:           0  
  Clock Path Skew:        -0.104ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.971ns = ( 15.974 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.345ns (routing 0.578ns, distribution 0.767ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.213     4.982    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X87Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.345    15.974    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X87Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]/C
                         clock pessimism             -0.382    15.591    
                         clock uncertainty           -0.076    15.516    
    SLICE_X87Y371        FDCE (Recov_EFF_SLICEM_C_CLR)
                                                     -0.066    15.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[2]
  -------------------------------------------------------------------
                         required time                         15.450    
                         arrival time                          -4.982    
  -------------------------------------------------------------------
                         slack                                 10.468    

Slack (MET) :             10.468ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.289ns  (logic 0.076ns (5.897%)  route 1.213ns (94.102%))
  Logic Levels:           0  
  Clock Path Skew:        -0.104ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.971ns = ( 15.974 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.345ns (routing 0.578ns, distribution 0.767ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.213     4.982    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X87Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.345    15.974    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X87Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]/C
                         clock pessimism             -0.382    15.591    
                         clock uncertainty           -0.076    15.516    
    SLICE_X87Y371        FDCE (Recov_EFF2_SLICEM_C_CLR)
                                                     -0.066    15.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[4]
  -------------------------------------------------------------------
                         required time                         15.450    
                         arrival time                          -4.982    
  -------------------------------------------------------------------
                         slack                                 10.468    

Slack (MET) :             10.477ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.277ns  (logic 0.076ns (5.953%)  route 1.201ns (94.047%))
  Logic Levels:           0  
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.968ns = ( 15.971 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.578ns, distribution 0.764ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.201     4.970    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X88Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.342    15.971    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X88Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/C
                         clock pessimism             -0.382    15.588    
                         clock uncertainty           -0.076    15.513    
    SLICE_X88Y371        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066    15.447    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]
  -------------------------------------------------------------------
                         required time                         15.447    
                         arrival time                          -4.970    
  -------------------------------------------------------------------
                         slack                                 10.477    

Slack (MET) :             10.477ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.277ns  (logic 0.076ns (5.953%)  route 1.201ns (94.047%))
  Logic Levels:           0  
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.968ns = ( 15.971 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.578ns, distribution 0.764ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.201     4.970    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X88Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.342    15.971    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X88Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/C
                         clock pessimism             -0.382    15.588    
                         clock uncertainty           -0.076    15.513    
    SLICE_X88Y371        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    15.447    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]
  -------------------------------------------------------------------
                         required time                         15.447    
                         arrival time                          -4.970    
  -------------------------------------------------------------------
                         slack                                 10.477    

Slack (MET) :             10.477ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.277ns  (logic 0.076ns (5.953%)  route 1.201ns (94.047%))
  Logic Levels:           0  
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.968ns = ( 15.971 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.578ns, distribution 0.764ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.201     4.970    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X88Y371        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.342    15.971    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X88Y371        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
                         clock pessimism             -0.382    15.588    
                         clock uncertainty           -0.076    15.513    
    SLICE_X88Y371        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    15.447    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg
  -------------------------------------------------------------------
                         required time                         15.447    
                         arrival time                          -4.970    
  -------------------------------------------------------------------
                         slack                                 10.477    

Slack (MET) :             10.477ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.277ns  (logic 0.076ns (5.953%)  route 1.201ns (94.047%))
  Logic Levels:           0  
  Clock Path Skew:        -0.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.968ns = ( 15.971 - 12.002 ) 
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    -0.382ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.578ns, distribution 0.764ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.201     4.970    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X88Y371        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    J19                                               0.000    12.002 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079    12.081    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475    12.556 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.596    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.596 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297    12.893    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    12.917 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850    13.767    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    14.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207    14.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    14.628 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.342    15.971    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X88Y371        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst_reg/C
                         clock pessimism             -0.382    15.588    
                         clock uncertainty           -0.076    15.513    
    SLICE_X88Y371        FDPE (Recov_BFF_SLICEL_C_PRE)
                                                     -0.066    15.447    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst_reg
  -------------------------------------------------------------------
                         required time                         15.447    
                         arrival time                          -4.970    
  -------------------------------------------------------------------
                         slack                                 10.477    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.116ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.760%)  route 0.067ns (63.240%))
  Logic Levels:           0  
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.236ns
    Source Clock Delay      (SCD):    2.389ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Net Delay (Source):      0.848ns (routing 0.349ns, distribution 0.499ns)
  Clock Net Delay (Destination): 0.961ns (routing 0.390ns, distribution 0.571ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.848     2.389    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X88Y370        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y370        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.428 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_abort_rd_reg/Q
                         net (fo=2, routed)           0.067     2.495    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clr_abort_rd
    SLICE_X88Y370        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.961     2.236    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/clk
    SLICE_X88Y370        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg/C
                         clock pessimism              0.162     2.399    
    SLICE_X88Y370        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     2.379    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_ABORT_FLAG/G_NEG_EDGE.flag_reg
  -------------------------------------------------------------------
                         required time                         -2.379    
                         arrival time                           2.495    
  -------------------------------------------------------------------
                         slack                                  0.116    

Slack (MET) :             0.142ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_rd_req_reg/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_REQ_FLAG/G_POS_EDGE.flag_reg/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.137ns  (logic 0.039ns (28.448%)  route 0.098ns (71.552%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.231ns
    Source Clock Delay      (SCD):    2.379ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Net Delay (Source):      0.838ns (routing 0.349ns, distribution 0.489ns)
  Clock Net Delay (Destination): 0.955ns (routing 0.390ns, distribution 0.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.838     2.379    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X89Y370        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_rd_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y370        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.418 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clr_rd_req_reg/Q
                         net (fo=2, routed)           0.098     2.516    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_REQ_FLAG/clr_rd_req
    SLICE_X89Y370        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_REQ_FLAG/G_POS_EDGE.flag_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.955     2.231    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_REQ_FLAG/clk
    SLICE_X89Y370        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_REQ_FLAG/G_POS_EDGE.flag_reg/C
                         clock pessimism              0.162     2.393    
    SLICE_X89Y370        FDCE (Remov_DFF2_SLICEM_C_CLR)
                                                     -0.020     2.373    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_RD_REQ_FLAG/G_POS_EDGE.flag_reg
  -------------------------------------------------------------------
                         required time                         -2.373    
                         arrival time                           2.516    
  -------------------------------------------------------------------
                         slack                                  0.142    

Slack (MET) :             0.167ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.039ns (24.375%)  route 0.121ns (75.625%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.230ns
    Source Clock Delay      (SCD):    2.379ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Net Delay (Source):      0.838ns (routing 0.349ns, distribution 0.489ns)
  Clock Net Delay (Destination): 0.954ns (routing 0.390ns, distribution 0.564ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.838     2.379    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X97Y341        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y341        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.418 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q
                         net (fo=1, routed)           0.121     2.539    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2
    SLICE_X98Y341        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.954     2.230    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X98Y341        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism              0.162     2.393    
    SLICE_X98Y341        FDPE (Remov_HFF2_SLICEL_C_PRE)
                                                     -0.020     2.373    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -2.373    
                         arrival time                           2.539    
  -------------------------------------------------------------------
                         slack                                  0.167    

Slack (MET) :             0.183ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.039ns (21.559%)  route 0.142ns (78.441%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.231ns
    Source Clock Delay      (SCD):    2.376ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Net Delay (Source):      0.835ns (routing 0.349ns, distribution 0.486ns)
  Clock Net Delay (Destination): 0.955ns (routing 0.390ns, distribution 0.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.835     2.376    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X98Y341        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y341        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.415 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.142     2.557    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X97Y341        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.955     2.231    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X97Y341        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg/C
                         clock pessimism              0.162     2.394    
    SLICE_X97Y341        FDPE (Remov_DFF2_SLICEM_C_PRE)
                                                     -0.020     2.374    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
  -------------------------------------------------------------------
                         required time                         -2.374    
                         arrival time                           2.557    
  -------------------------------------------------------------------
                         slack                                  0.183    

Slack (MET) :             0.183ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.039ns (21.559%)  route 0.142ns (78.441%))
  Logic Levels:           0  
  Clock Path Skew:        0.017ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.231ns
    Source Clock Delay      (SCD):    2.376ns
    Clock Pessimism Removal (CPR):    -0.162ns
  Clock Net Delay (Source):      0.835ns (routing 0.349ns, distribution 0.486ns)
  Clock Net Delay (Destination): 0.955ns (routing 0.390ns, distribution 0.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.835     2.376    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X98Y341        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y341        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.415 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/rddata_rst_reg/Q
                         net (fo=20, routed)          0.142     2.557    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X97Y341        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.955     2.231    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X97Y341        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                         clock pessimism              0.162     2.394    
    SLICE_X97Y341        FDPE (Remov_AFF2_SLICEM_C_PRE)
                                                     -0.020     2.374    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
  -------------------------------------------------------------------
                         required time                         -2.374    
                         arrival time                           2.557    
  -------------------------------------------------------------------
                         slack                                  0.183    

Slack (MET) :             0.210ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.265ns  (logic 0.039ns (14.710%)  route 0.226ns (85.290%))
  Logic Levels:           0  
  Clock Path Skew:        0.076ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.226ns
    Source Clock Delay      (SCD):    2.375ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      0.834ns (routing 0.349ns, distribution 0.485ns)
  Clock Net Delay (Destination): 0.951ns (routing 0.390ns, distribution 0.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.834     2.375    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X98Y347        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y347        FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.414 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.226     2.640    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/AR[0]
    SLICE_X95Y361        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.951     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X95Y361        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/C
                         clock pessimism              0.224     2.451    
    SLICE_X95Y361        FDCE (Remov_FFF2_SLICEL_C_CLR)
                                                     -0.020     2.431    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.431    
                         arrival time                           2.640    
  -------------------------------------------------------------------
                         slack                                  0.210    

Slack (MET) :             0.210ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].wr_stg_inst/Q_reg_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.265ns  (logic 0.039ns (14.710%)  route 0.226ns (85.290%))
  Logic Levels:           0  
  Clock Path Skew:        0.076ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.226ns
    Source Clock Delay      (SCD):    2.375ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      0.834ns (routing 0.349ns, distribution 0.485ns)
  Clock Net Delay (Destination): 0.951ns (routing 0.390ns, distribution 0.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.834     2.375    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X98Y347        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y347        FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.414 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.226     2.640    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].wr_stg_inst/AR[0]
    SLICE_X95Y361        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].wr_stg_inst/Q_reg_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.951     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].wr_stg_inst/wr_clk
    SLICE_X95Y361        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].wr_stg_inst/Q_reg_reg[0]/C
                         clock pessimism              0.224     2.451    
    SLICE_X95Y361        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     2.431    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.431    
                         arrival time                           2.640    
  -------------------------------------------------------------------
                         slack                                  0.210    

Slack (MET) :             0.210ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.265ns  (logic 0.039ns (14.710%)  route 0.226ns (85.290%))
  Logic Levels:           0  
  Clock Path Skew:        0.076ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.226ns
    Source Clock Delay      (SCD):    2.375ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      0.834ns (routing 0.349ns, distribution 0.485ns)
  Clock Net Delay (Destination): 0.951ns (routing 0.390ns, distribution 0.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.834     2.375    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X98Y347        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y347        FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.414 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.226     2.640    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/AR[0]
    SLICE_X95Y361        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.951     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X95Y361        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[0]/C
                         clock pessimism              0.224     2.451    
    SLICE_X95Y361        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     2.431    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.431    
                         arrival time                           2.640    
  -------------------------------------------------------------------
                         slack                                  0.210    

Slack (MET) :             0.210ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.265ns  (logic 0.039ns (14.710%)  route 0.226ns (85.290%))
  Logic Levels:           0  
  Clock Path Skew:        0.076ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.226ns
    Source Clock Delay      (SCD):    2.375ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      0.834ns (routing 0.349ns, distribution 0.485ns)
  Clock Net Delay (Destination): 0.951ns (routing 0.390ns, distribution 0.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.834     2.375    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X98Y347        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y347        FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.414 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.226     2.640    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/AR[0]
    SLICE_X95Y361        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.951     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X95Y361        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[1]/C
                         clock pessimism              0.224     2.451    
    SLICE_X95Y361        FDCE (Remov_GFF2_SLICEL_C_CLR)
                                                     -0.020     2.431    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.431    
                         arrival time                           2.640    
  -------------------------------------------------------------------
                         slack                                  0.210    

Slack (MET) :             0.210ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.265ns  (logic 0.039ns (14.710%)  route 0.226ns (85.290%))
  Logic Levels:           0  
  Clock Path Skew:        0.076ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.226ns
    Source Clock Delay      (SCD):    2.375ns
    Clock Pessimism Removal (CPR):    -0.224ns
  Clock Net Delay (Source):      0.834ns (routing 0.349ns, distribution 0.485ns)
  Clock Net Delay (Destination): 0.951ns (routing 0.390ns, distribution 0.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.834     2.375    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X98Y347        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X98Y347        FDPE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.414 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.226     2.640    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/AR[0]
    SLICE_X95Y361        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.951     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X95Y361        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[2]/C
                         clock pessimism              0.224     2.451    
    SLICE_X95Y361        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     2.431    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.431    
                         arrival time                           2.640    
  -------------------------------------------------------------------
                         slack                                  0.210    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.881ns  (logic 0.938ns (24.171%)  route 2.943ns (75.829%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.705ns (routing 1.446ns, distribution 1.259ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.705     3.378    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y247        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y247        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.457 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           2.943     6.400    PMOD0_1_LS_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.859     7.259 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     7.259    PMOD0_1_LS
    M18                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.514ns  (logic 0.938ns (26.695%)  route 2.576ns (73.305%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.715ns (routing 1.446ns, distribution 1.269ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.715     3.388    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y200        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y200        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.467 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           2.576     6.043    PMOD0_7_LS_OBUF
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.859     6.902 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.902    PMOD0_7_LS
    J15                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.410ns  (logic 0.943ns (27.652%)  route 2.467ns (72.348%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.730ns (routing 1.446ns, distribution 1.284ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.730     3.403    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X66Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y202        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.481 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           2.467     5.948    PMOD0_3_LS_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.865     6.813 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.813    PMOD0_3_LS
    H17                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.353ns  (logic 0.945ns (28.178%)  route 2.408ns (71.822%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.686ns (routing 1.446ns, distribution 1.240ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.686     3.359    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X62Y243        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y243        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.438 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           2.408     5.846    PMOD0_2_LS_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.866     6.712 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.712    PMOD0_2_LS
    H16                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.342ns  (logic 0.938ns (28.072%)  route 2.404ns (71.928%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.684ns (routing 1.446ns, distribution 1.238ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.684     3.357    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X62Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y208        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.436 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           2.404     5.840    PMOD0_6_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.859     6.699 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.699    PMOD0_6_LS
    H15                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.323ns  (logic 0.949ns (28.548%)  route 2.374ns (71.452%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.691ns (routing 1.446ns, distribution 1.245ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.691     3.364    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X62Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y207        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.443 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           2.374     5.817    PMOD0_4_LS_OBUF
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.870     6.687 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.687    PMOD0_4_LS
    J16                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.291ns  (logic 0.926ns (28.153%)  route 2.364ns (71.847%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.706ns (routing 1.446ns, distribution 1.260ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.706     3.379    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y242        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y242        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     3.458 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           2.364     5.822    PMOD0_0_LS_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.847     6.670 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.670    PMOD0_0_LS
    C17                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        3.273ns  (logic 0.948ns (28.959%)  route 2.325ns (71.041%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.706ns (routing 1.446ns, distribution 1.260ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.706     3.379    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y212        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     3.458 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           2.325     5.783    PMOD0_5_LS_OBUF
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.869     6.652 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     6.652    PMOD0_5_LS
    K16                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_0_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.603ns  (logic 0.460ns (28.696%)  route 1.143ns (71.304%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.475ns (routing 0.779ns, distribution 0.696ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.475     1.824    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y242        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y242        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.863 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=2, routed)           1.143     3.006    PMOD0_0_LS_OBUF
    C17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.421     3.427 r  PMOD0_0_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.427    PMOD0_0_LS
    C17                                                               r  PMOD0_0_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_5_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.603ns  (logic 0.481ns (30.016%)  route 1.122ns (69.984%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.478ns (routing 0.779ns, distribution 0.699ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.478     1.827    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y212        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.866 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           1.122     2.988    PMOD0_5_LS_OBUF
    K16                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.442     3.430 r  PMOD0_5_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.430    PMOD0_5_LS
    K16                                                               r  PMOD0_5_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_6_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.632ns  (logic 0.472ns (28.898%)  route 1.161ns (71.102%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.467ns (routing 0.779ns, distribution 0.688ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.467     1.816    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X62Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y208        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.855 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           1.161     3.016    PMOD0_6_LS_OBUF
    H15                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.433     3.448 r  PMOD0_6_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.448    PMOD0_6_LS
    H15                                                               r  PMOD0_6_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_4_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.632ns  (logic 0.482ns (29.537%)  route 1.150ns (70.463%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.471ns (routing 0.779ns, distribution 0.692ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.471     1.820    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X62Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y207        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.859 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           1.150     3.009    PMOD0_4_LS_OBUF
    J16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.443     3.452 r  PMOD0_4_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.452    PMOD0_4_LS
    J16                                                               r  PMOD0_4_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_2_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.646ns  (logic 0.478ns (29.051%)  route 1.168ns (70.949%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.466ns (routing 0.779ns, distribution 0.687ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.466     1.815    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X62Y243        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y243        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.854 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           1.168     3.022    PMOD0_2_LS_OBUF
    H16                  OBUF (Prop_OUTBUF_HPIOB_S_I_O)
                                                      0.439     3.461 r  PMOD0_2_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.461    PMOD0_2_LS
    H16                                                               r  PMOD0_2_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_3_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.666ns  (logic 0.477ns (28.653%)  route 1.189ns (71.347%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.490ns (routing 0.779ns, distribution 0.711ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.490     1.839    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X66Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y202        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.878 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           1.189     3.067    PMOD0_3_LS_OBUF
    H17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.438     3.505 r  PMOD0_3_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.505    PMOD0_3_LS
    H17                                                               r  PMOD0_3_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_7_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.738ns  (logic 0.472ns (27.131%)  route 1.267ns (72.869%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.483ns (routing 0.779ns, distribution 0.704ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.483     1.832    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y200        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y200        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.871 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           1.267     3.138    PMOD0_7_LS_OBUF
    J15                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.433     3.570 r  PMOD0_7_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.570    PMOD0_7_LS
    J15                                                               r  PMOD0_7_LS (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            PMOD0_1_LS
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.911ns  (logic 0.472ns (24.686%)  route 1.439ns (75.314%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.475ns (routing 0.779ns, distribution 0.696ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.475     1.824    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X65Y247        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y247        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.863 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           1.439     3.302    PMOD0_1_LS_OBUF
    M18                  OBUF (Prop_OUTBUF_HPIOB_SNGL_I_O)
                                                      0.433     3.735 r  PMOD0_1_LS_OBUF_inst/O
                         net (fo=0)                   0.000     3.735    PMOD0_1_LS
    M18                                                               r  PMOD0_1_LS (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFADC0_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.110ns  (logic 0.090ns (4.265%)  route 2.020ns (95.735%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.671ns (routing 1.682ns, distribution 0.989ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.695     1.695    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X55Y251        LUT1 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.090     1.785 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.325     2.110    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X52Y256        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          2.671     3.057    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X52Y256        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.031ns  (logic 0.036ns (3.493%)  route 0.995ns (96.507%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.841ns (routing 1.125ns, distribution 0.716ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.849     0.849    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X55Y251        LUT1 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     0.885 r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.146     1.031    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X52Y256        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
    X3Y5 (CLOCK_ROOT)    net (fo=35, routed)          1.841     2.193    d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X52Y256        FDRE                                         r  d_1_i/rst_adc0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC1_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.473ns  (logic 0.110ns (4.448%)  route 2.363ns (95.552%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.335ns (routing 1.313ns, distribution 1.022ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.929     1.929    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X52Y258        LUT1 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.110     2.039 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.434     2.473    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X51Y265        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.335     2.856    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X51Y265        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.205ns  (logic 0.038ns (3.155%)  route 1.167ns (96.845%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.596ns (routing 0.870ns, distribution 0.726ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.970     0.970    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X52Y258        LUT1 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.038     1.008 r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.197     1.205    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X51Y265        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.596     2.044    d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X51Y265        FDRE                                         r  d_1_i/rst_dac0/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  RFDAC1_CLK

Max Delay          8576 Endpoints
Min Delay          8576 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[65]_INST_0_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.285ns  (logic 0.257ns (5.997%)  route 4.028ns (94.003%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.141ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.164ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.643ns (routing 1.313ns, distribution 1.330ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.169     5.920    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/SR[0]
    SLICE_X107Y278       LUT1 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     6.070 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[78]_INST_0_psdsp_inv/O
                         net (fo=16, routed)          1.520     7.590    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[78]_INST_0_psdsp_inv_n
    SLICE_X103Y284       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[65]_INST_0_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.643     3.164    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/aclk
    SLICE_X103Y284       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[65]_INST_0_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[72]_INST_0_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.285ns  (logic 0.257ns (5.997%)  route 4.028ns (94.003%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.141ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.164ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.643ns (routing 1.313ns, distribution 1.330ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.169     5.920    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/SR[0]
    SLICE_X107Y278       LUT1 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     6.070 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[78]_INST_0_psdsp_inv/O
                         net (fo=16, routed)          1.520     7.590    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[78]_INST_0_psdsp_inv_n
    SLICE_X103Y284       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[72]_INST_0_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.643     3.164    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/aclk
    SLICE_X103Y284       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[72]_INST_0_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_10_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.238ns  (logic 0.255ns (6.018%)  route 3.983ns (93.982%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.179ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.126ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.605ns (routing 1.313ns, distribution 1.292ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.093     5.844    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/SR[0]
    SLICE_X83Y319        LUT1 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.148     5.992 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[143]_INST_0_psdsp_psdsp_inv/O
                         net (fo=16, routed)          1.551     7.543    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/m_axis_tdata[143]_INST_0_psdsp_psdsp_inv_n_alias
    SLICE_X83Y314        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_10_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.605     3.126    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/aclk
    SLICE_X83Y314        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_10_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_8_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.238ns  (logic 0.255ns (6.018%)  route 3.983ns (93.982%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.179ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.126ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.605ns (routing 1.313ns, distribution 1.292ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.093     5.844    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/SR[0]
    SLICE_X83Y319        LUT1 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.148     5.992 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[143]_INST_0_psdsp_psdsp_inv/O
                         net (fo=16, routed)          1.551     7.543    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/m_axis_tdata[143]_INST_0_psdsp_psdsp_inv_n_alias
    SLICE_X83Y314        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_8_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.605     3.126    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/aclk
    SLICE_X83Y314        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_8_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_1_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.083ns  (logic 0.232ns (5.682%)  route 3.851ns (94.318%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.161ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.144ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.623ns (routing 1.313ns, distribution 1.310ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.340     6.091    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/SR[0]
    SLICE_X75Y364        LUT1 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.125     6.216 r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[143]_INST_0_psdsp_psdsp_inv/O
                         net (fo=16, routed)          1.172     7.388    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/m_axis_tdata[143]_INST_0_psdsp_psdsp_inv_n_alias
    SLICE_X84Y360        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_1_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.623     3.144    d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/aclk
    SLICE_X84Y360        FDRE                                         r  d_1_i/axis_signal_gen_v6_6/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[66]_INST_0_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.018ns  (logic 0.257ns (6.396%)  route 3.761ns (93.604%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.209ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.688ns (routing 1.313ns, distribution 1.375ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.169     5.920    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/SR[0]
    SLICE_X107Y278       LUT1 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.150     6.070 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[78]_INST_0_psdsp_inv/O
                         net (fo=16, routed)          1.253     7.323    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[78]_INST_0_psdsp_inv_n
    SLICE_X110Y285       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[66]_INST_0_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.688     3.209    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/aclk
    SLICE_X110Y285       FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[66]_INST_0_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_1_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.988ns  (logic 0.255ns (6.394%)  route 3.733ns (93.606%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.318ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.987ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.466ns (routing 1.313ns, distribution 1.153ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.093     5.844    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/SR[0]
    SLICE_X83Y319        LUT1 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.148     5.992 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[143]_INST_0_psdsp_psdsp_inv/O
                         net (fo=16, routed)          1.301     7.293    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/m_axis_tdata[143]_INST_0_psdsp_psdsp_inv_n_alias
    SLICE_X65Y318        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_1_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.466     2.987    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/aclk
    SLICE_X65Y318        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[8].prodg_y_full_real_r_reg[8]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[15].prodg_y_full_real_r_reg[15]_i_1_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.949ns  (logic 0.205ns (5.191%)  route 3.744ns (94.809%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.232ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.073ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.552ns (routing 1.313ns, distribution 1.239ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.149     5.900    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X74Y265        LUT1 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.098     5.998 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].last_r_reg[0][15]_psdsp_inv/O
                         net (fo=16, routed)          1.256     7.254    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[0].last_r_reg[0][15]_psdsp_inv_n_alias
    SLICE_X82Y262        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[15].prodg_y_full_real_r_reg[15]_i_1_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.552     3.073    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/aclk
    SLICE_X82Y262        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[15].prodg_y_full_real_r_reg[15]_i_1_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q_reg[3]_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.929ns  (logic 0.231ns (5.879%)  route 3.698ns (94.121%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.342ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.963ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.442ns (routing 1.313ns, distribution 1.129ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.487     6.238    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X33Y223        LUT1 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.124     6.362 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prod_y_r2_reg[0][15]_psdsp_inv/O
                         net (fo=16, routed)          0.872     7.234    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/GEN_dds[0].prod_y_r2_reg[0][15]_psdsp_inv_n_alias
    SLICE_X28Y216        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q_reg[3]_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.442     2.963    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/aclk
    SLICE_X28Y216        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_piped_map.i_cardinal_sin_ms/opt_has_pipe.first_q_reg[3]_psdsp/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[4].prodg_y_full_real_r_reg[4]_i_16_psdsp/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.924ns  (logic 0.144ns (3.670%)  route 3.780ns (96.330%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.094ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.573ns (routing 1.313ns, distribution 1.260ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.077     5.828    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/SR[0]
    SLICE_X89Y244        LUT1 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.037     5.865 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[79]_INST_0_psdsp_psdsp_inv/O
                         net (fo=16, routed)          1.364     7.229    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/m_axis_tdata[79]_INST_0_psdsp_psdsp_inv_n_alias
    SLICE_X83Y240        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[4].prodg_y_full_real_r_reg[4]_i_16_psdsp/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.573     3.094    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/aclk
    SLICE_X83Y240        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/src_latency_reg_i/GEN_dds[4].prodg_y_full_real_r_reg[4]_i_16_psdsp/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][12]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.332ns  (logic 0.056ns (4.204%)  route 1.276ns (95.796%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.175ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.870ns, distribution 0.857ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.567     3.110    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/SR[0]
    SLICE_X81Y274        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][12]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.727     2.175    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/aclk
    SLICE_X81Y274        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][12]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][13]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.332ns  (logic 0.056ns (4.204%)  route 1.276ns (95.796%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.175ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.870ns, distribution 0.857ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.567     3.110    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/SR[0]
    SLICE_X81Y274        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][13]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.727     2.175    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/aclk
    SLICE_X81Y274        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][13]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][2]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.332ns  (logic 0.056ns (4.204%)  route 1.276ns (95.796%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.175ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.870ns, distribution 0.857ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.567     3.110    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/SR[0]
    SLICE_X81Y274        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][2]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.727     2.175    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/aclk
    SLICE_X81Y274        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][2]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][3]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.332ns  (logic 0.056ns (4.204%)  route 1.276ns (95.796%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.175ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.727ns (routing 0.870ns, distribution 0.857ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.567     3.110    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/SR[0]
    SLICE_X81Y274        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][3]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.727     2.175    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/aclk
    SLICE_X81Y274        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/gain_latency_reg_i/GEN_reg[15].shift_r_reg[15][3]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/RSTA
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.336ns  (logic 0.056ns (4.192%)  route 1.280ns (95.808%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.428ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.206ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.758ns (routing 0.870ns, distribution 0.888ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.571     3.114    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/RSTA
    DSP48E2_X15Y108      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/RSTA  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.758     2.206    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/CLK
    DSP48E2_X15Y108      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/RSTB
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.336ns  (logic 0.056ns (4.192%)  route 1.280ns (95.808%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.428ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.206ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.758ns (routing 0.870ns, distribution 0.888ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.571     3.114    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/RSTB
    DSP48E2_X15Y108      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/RSTB  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.758     2.206    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/CLK
    DSP48E2_X15Y108      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_A_B_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_OUTPUT_INST/RSTP
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.338ns  (logic 0.056ns (4.185%)  route 1.282ns (95.815%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.428ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.206ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.758ns (routing 0.870ns, distribution 0.888ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.573     3.116    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/RSTP
    DSP48E2_X15Y108      DSP_OUTPUT                                   r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_OUTPUT_INST/RSTP  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.758     2.206    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/CLK
    DSP48E2_X15Y108      DSP_OUTPUT                                   r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[5].prodg_y_full_real_r_reg[5]/DSP_OUTPUT_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_A_B_DATA_INST/RSTB
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.340ns  (logic 0.056ns (4.179%)  route 1.284ns (95.821%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.440ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.218ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.770ns (routing 0.870ns, distribution 0.900ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.575     3.118    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/RSTB
    DSP48E2_X15Y106      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_A_B_DATA_INST/RSTB  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.770     2.218    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/CLK
    DSP48E2_X15Y106      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_A_B_DATA_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/RSTP
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.340ns  (logic 0.056ns (4.179%)  route 1.284ns (95.821%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.440ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.218ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.770ns (routing 0.870ns, distribution 0.900ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.575     3.118    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/RSTP
    DSP48E2_X15Y106      DSP_OUTPUT                                   r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/RSTP  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.770     2.218    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/CLK
    DSP48E2_X15Y106      DSP_OUTPUT                                   r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_OUTPUT_INST/CLK

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_A_B_DATA_INST/RSTA
                            (rising edge-triggered cell DSP_A_B_DATA clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.342ns  (logic 0.056ns (4.173%)  route 1.286ns (95.827%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.440ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.218ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.770ns (routing 0.870ns, distribution 0.900ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 f  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.577     3.120    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/RSTA
    DSP48E2_X15Y106      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_A_B_DATA_INST/RSTA  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.770     2.218    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/CLK
    DSP48E2_X15Y106      DSP_A_B_DATA                                 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[0].prodg_y_full_real_r_reg[0]/DSP_A_B_DATA_INST/CLK





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  RFDAC1_CLK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.387ns  (logic 0.236ns (17.021%)  route 1.151ns (82.979%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -3.614ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.879ns
    Source Clock Delay      (SCD):    6.493ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.991ns (routing 1.562ns, distribution 1.429ns)
  Clock Net Delay (Destination): 2.358ns (routing 1.313ns, distribution 1.045ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.991     6.493    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X67Y241        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y241        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     6.572 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=202, routed)         0.785     7.356    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[2]
    SLICE_X62Y251        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     7.513 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.366     7.879    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.358     2.879    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.124ns  (logic 0.209ns (18.587%)  route 0.915ns (81.413%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -3.616ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.877ns
    Source Clock Delay      (SCD):    6.493ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.991ns (routing 1.562ns, distribution 1.429ns)
  Clock Net Delay (Destination): 2.356ns (routing 1.313ns, distribution 1.043ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.991     6.493    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X67Y241        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y241        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     6.569 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=203, routed)         0.900     7.469    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[3]
    SLICE_X59Y251        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.133     7.602 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.015     7.617    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.356     2.877    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.008ns  (logic 0.076ns (7.537%)  route 0.932ns (92.463%))
  Logic Levels:           0  
  Clock Path Skew:        -3.614ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.879ns
    Source Clock Delay      (SCD):    6.493ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.991ns (routing 1.562ns, distribution 1.429ns)
  Clock Net Delay (Destination): 2.358ns (routing 1.313ns, distribution 1.045ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.991     6.493    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X67Y241        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y241        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     6.569 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=203, routed)         0.932     7.501    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[3]
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.358     2.879    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.037ns  (logic 0.127ns (12.247%)  route 0.910ns (87.753%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -3.508ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.879ns
    Source Clock Delay      (SCD):    6.387ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.885ns (routing 1.562ns, distribution 1.323ns)
  Clock Net Delay (Destination): 2.358ns (routing 1.313ns, distribution 1.045ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.885     6.387    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X63Y214        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y214        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     6.464 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=258, routed)         0.597     7.061    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[1]
    SLICE_X62Y251        LUT2 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     7.111 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=2, routed)           0.313     7.424    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.358     2.879    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.428ns  (logic 0.059ns (13.799%)  route 0.369ns (86.201%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.789ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.056ns
    Source Clock Delay      (SCD):    3.845ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.639ns (routing 0.858ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.608ns (routing 0.870ns, distribution 0.738ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.639     3.845    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X67Y241        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y241        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     3.884 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=202, routed)         0.363     4.247    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[2]
    SLICE_X59Y251        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.020     4.267 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.006     4.273    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.608     2.056    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.471ns  (logic 0.073ns (15.492%)  route 0.398ns (84.508%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.758ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.060ns
    Source Clock Delay      (SCD):    3.818ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.612ns (routing 0.858ns, distribution 0.754ns)
  Clock Net Delay (Destination): 1.612ns (routing 0.870ns, distribution 0.742ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.612     3.818    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X67Y238        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y238        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     3.856 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/Q
                         net (fo=258, routed)         0.262     4.118    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[0]
    SLICE_X62Y251        LUT2 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.035     4.153 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=2, routed)           0.137     4.289    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.612     2.060    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.513ns  (logic 0.058ns (11.299%)  route 0.455ns (88.701%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -1.736ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.060ns
    Source Clock Delay      (SCD):    3.796ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.590ns (routing 0.858ns, distribution 0.732ns)
  Clock Net Delay (Destination): 1.612ns (routing 0.870ns, distribution 0.742ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.590     3.796    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X63Y214        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y214        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     3.834 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=258, routed)         0.312     4.146    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[1]
    SLICE_X62Y251        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.020     4.166 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.143     4.309    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.612     2.060    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.488ns  (logic 0.037ns (7.584%)  route 0.451ns (92.416%))
  Logic Levels:           0  
  Clock Path Skew:        -1.785ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.060ns
    Source Clock Delay      (SCD):    3.845ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.639ns (routing 0.858ns, distribution 0.781ns)
  Clock Net Delay (Destination): 1.612ns (routing 0.870ns, distribution 0.742ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.639     3.845    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X67Y241        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y241        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     3.882 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=203, routed)         0.451     4.333    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[3]
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.612     2.060    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y251        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  RFDAC1_CLK

Max Delay           532 Endpoints
Min Delay           532 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.992ns  (logic 0.556ns (13.927%)  route 3.436ns (86.073%))
  Logic Levels:           6  (LUT4=2 LUT5=2 LUT6=2)
  Clock Path Skew:        -2.629ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.871ns
    Source Clock Delay      (SCD):    5.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.885ns (routing 1.611ns, distribution 1.274ns)
  Clock Net Delay (Destination): 2.350ns (routing 1.313ns, distribution 1.037ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.885     5.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X63Y290        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y290        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     5.579 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[5]/Q
                         net (fo=1, routed)           0.174     5.753    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/out[5]
    SLICE_X63Y290        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.152     5.905 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_4__11/O
                         net (fo=3, routed)           0.105     6.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_4__11_n_0
    SLICE_X62Y290        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     6.045 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/FSM_sequential_core_st[2]_i_7/O
                         net (fo=2, routed)           0.671     6.716    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/reg_D[0][14]_i_19_2
    SLICE_X57Y241        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     6.766 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/core_en_i_5/O
                         net (fo=3, routed)           0.439     7.205    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_1
    SLICE_X46Y229        LUT4 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.051     7.256 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/core_en_i_1/O
                         net (fo=3, routed)           0.046     7.302    d_1_i/qick_processor_0/inst/QPROC/some_fifo_full
    SLICE_X46Y229        LUT4 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     7.341 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=457, routed)         1.016     8.356    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/E[0]
    SLICE_X29Y231        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.150     8.506 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.986     9.492    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X47Y244        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.350     2.871    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X47Y244        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.355ns  (logic 0.580ns (17.285%)  route 2.775ns (82.715%))
  Logic Levels:           8  (LUT3=2 LUT4=2 LUT5=2 LUT6=2)
  Clock Path Skew:        -2.636ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.864ns
    Source Clock Delay      (SCD):    5.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.885ns (routing 1.611ns, distribution 1.274ns)
  Clock Net Delay (Destination): 2.343ns (routing 1.313ns, distribution 1.030ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.885     5.500    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X63Y290        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y290        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     5.579 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_r_reg[5]/Q
                         net (fo=1, routed)           0.174     5.753    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/out[5]
    SLICE_X63Y290        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.152     5.905 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_4__11/O
                         net (fo=3, routed)           0.105     6.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/RAM_reg_i_4__11_n_0
    SLICE_X62Y290        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     6.045 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/FSM_sequential_core_st[2]_i_7/O
                         net (fo=2, routed)           0.671     6.716    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/reg_D[0][14]_i_19_2
    SLICE_X57Y241        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     6.766 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[2].wave_fifo_inst/gcc_wr_ptr/core_en_i_5/O
                         net (fo=3, routed)           0.439     7.205    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_1
    SLICE_X46Y229        LUT4 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.051     7.256 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_wr_ptr/core_en_i_1/O
                         net (fo=3, routed)           0.046     7.302    d_1_i/qick_processor_0/inst/QPROC/some_fifo_full
    SLICE_X46Y229        LUT4 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     7.341 r  d_1_i/qick_processor_0/inst/QPROC/core_en/O
                         net (fo=457, routed)         0.360     7.701    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/E[0]
    SLICE_X43Y227        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.035     7.736 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_2/O
                         net (fo=4, routed)           0.251     7.987    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][5]_0
    SLICE_X41Y224        LUT3 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     8.038 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=34, routed)          0.223     8.260    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/time_updt_core
    SLICE_X39Y227        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     8.348 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[3]_i_1/O
                         net (fo=1, routed)           0.507     8.855    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[6]_0[3]
    SLICE_X47Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.343     2.864    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X47Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.401ns  (logic 0.166ns (6.913%)  route 2.235ns (93.087%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -2.331ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.871ns
    Source Clock Delay      (SCD):    5.202ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.587ns (routing 1.611ns, distribution 0.976ns)
  Clock Net Delay (Destination): 2.350ns (routing 1.313ns, distribution 1.037ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.587     5.202    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X23Y196        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X23Y196        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     5.278 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[12]/Q
                         net (fo=2, routed)           0.756     6.034    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r[12]
    SLICE_X8Y219         LUT4 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.090     6.124 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[0]_i_1/O
                         net (fo=1, routed)           1.479     7.603    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[6]_0[0]
    SLICE_X47Y244        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.350     2.871    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/t_clk_i
    SLICE_X47Y244        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/sync_ctrl_ps_t/data_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.519ns  (logic 0.355ns (23.373%)  route 1.164ns (76.627%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.516ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.979ns
    Source Clock Delay      (SCD):    5.495ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.880ns (routing 1.611ns, distribution 1.269ns)
  Clock Net Delay (Destination): 2.458ns (routing 1.313ns, distribution 1.145ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.880     5.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X64Y290        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y290        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.574 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.256     5.830    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req
    SLICE_X65Y290        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.987 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_fifo_data_empty_inferred_i_1/O
                         net (fo=1, routed)           0.149     6.136    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r_reg[0]
    SLICE_X65Y290        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.171 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.264     6.435    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r_reg[0]_0
    SLICE_X65Y298        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     6.484 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.136     6.620    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop
    SLICE_X65Y301        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     6.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__23/O
                         net (fo=18, routed)          0.358     7.014    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X62Y301        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.458     2.979    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X62Y301        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.515ns  (logic 0.355ns (23.435%)  route 1.160ns (76.565%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.508ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.987ns
    Source Clock Delay      (SCD):    5.495ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.880ns (routing 1.611ns, distribution 1.269ns)
  Clock Net Delay (Destination): 2.466ns (routing 1.313ns, distribution 1.153ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.880     5.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X64Y290        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y290        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.574 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.256     5.830    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req
    SLICE_X65Y290        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.987 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_fifo_data_empty_inferred_i_1/O
                         net (fo=1, routed)           0.149     6.136    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r_reg[0]
    SLICE_X65Y290        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.171 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.264     6.435    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r_reg[0]_0
    SLICE_X65Y298        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     6.484 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.136     6.620    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop
    SLICE_X65Y301        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     6.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__23/O
                         net (fo=18, routed)          0.354     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.466     2.987    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.515ns  (logic 0.355ns (23.435%)  route 1.160ns (76.565%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.508ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.987ns
    Source Clock Delay      (SCD):    5.495ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.880ns (routing 1.611ns, distribution 1.269ns)
  Clock Net Delay (Destination): 2.466ns (routing 1.313ns, distribution 1.153ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.880     5.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X64Y290        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y290        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.574 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.256     5.830    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req
    SLICE_X65Y290        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.987 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_fifo_data_empty_inferred_i_1/O
                         net (fo=1, routed)           0.149     6.136    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r_reg[0]
    SLICE_X65Y290        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.171 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.264     6.435    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r_reg[0]_0
    SLICE_X65Y298        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     6.484 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.136     6.620    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop
    SLICE_X65Y301        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     6.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__23/O
                         net (fo=18, routed)          0.354     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.466     2.987    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.515ns  (logic 0.355ns (23.435%)  route 1.160ns (76.565%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.508ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.987ns
    Source Clock Delay      (SCD):    5.495ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.880ns (routing 1.611ns, distribution 1.269ns)
  Clock Net Delay (Destination): 2.466ns (routing 1.313ns, distribution 1.153ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.880     5.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X64Y290        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y290        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.574 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.256     5.830    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req
    SLICE_X65Y290        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.987 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_fifo_data_empty_inferred_i_1/O
                         net (fo=1, routed)           0.149     6.136    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r_reg[0]
    SLICE_X65Y290        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.171 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.264     6.435    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r_reg[0]_0
    SLICE_X65Y298        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     6.484 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.136     6.620    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop
    SLICE_X65Y301        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     6.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__23/O
                         net (fo=18, routed)          0.354     7.010    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.466     2.987    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.496ns  (logic 0.355ns (23.723%)  route 1.141ns (76.277%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.507ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.988ns
    Source Clock Delay      (SCD):    5.495ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.880ns (routing 1.611ns, distribution 1.269ns)
  Clock Net Delay (Destination): 2.467ns (routing 1.313ns, distribution 1.154ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.880     5.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X64Y290        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y290        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.574 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.256     5.830    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req
    SLICE_X65Y290        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.987 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_fifo_data_empty_inferred_i_1/O
                         net (fo=1, routed)           0.149     6.136    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r_reg[0]
    SLICE_X65Y290        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.171 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.264     6.435    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r_reg[0]_0
    SLICE_X65Y298        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     6.484 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.136     6.620    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop
    SLICE_X65Y301        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     6.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__23/O
                         net (fo=18, routed)          0.336     6.991    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.467     2.988    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.496ns  (logic 0.355ns (23.723%)  route 1.141ns (76.277%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.507ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.988ns
    Source Clock Delay      (SCD):    5.495ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.880ns (routing 1.611ns, distribution 1.269ns)
  Clock Net Delay (Destination): 2.467ns (routing 1.313ns, distribution 1.154ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.880     5.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X64Y290        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y290        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.574 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.256     5.830    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req
    SLICE_X65Y290        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.987 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_fifo_data_empty_inferred_i_1/O
                         net (fo=1, routed)           0.149     6.136    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r_reg[0]
    SLICE_X65Y290        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.171 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.264     6.435    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r_reg[0]_0
    SLICE_X65Y298        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     6.484 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.136     6.620    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop
    SLICE_X65Y301        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     6.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__23/O
                         net (fo=18, routed)          0.336     6.991    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.467     2.988    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.496ns  (logic 0.355ns (23.723%)  route 1.141ns (76.277%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -2.507ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.988ns
    Source Clock Delay      (SCD):    5.495ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.880ns (routing 1.611ns, distribution 1.269ns)
  Clock Net Delay (Destination): 2.467ns (routing 1.313ns, distribution 1.154ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.880     5.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X64Y290        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y290        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.574 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.256     5.830    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/clr_fifo_req
    SLICE_X65Y290        LUT3 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.157     5.987 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_fifo_data_empty_inferred_i_1/O
                         net (fo=1, routed)           0.149     6.136    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r_reg[0]
    SLICE_X65Y290        LUT5 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     6.171 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop_r[0]_i_2/O
                         net (fo=1, routed)           0.264     6.435    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r_reg[0]_0
    SLICE_X65Y298        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     6.484 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/data_pop_r[0]_i_1/O
                         net (fo=2, routed)           0.136     6.620    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/data_pop
    SLICE_X65Y301        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     6.655 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__23/O
                         net (fo=18, routed)          0.336     6.991    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.467     2.988    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_r_reg[7]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.207%)  route 0.060ns (60.793%))
  Logic Levels:           0  
  Clock Path Skew:        -1.174ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.065ns
    Source Clock Delay      (SCD):    3.240ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.500ns (routing 0.877ns, distribution 0.623ns)
  Clock Net Delay (Destination): 1.617ns (routing 0.870ns, distribution 0.747ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.500     3.240    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y205        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y205        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     3.279 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/Q
                         net (fo=2, routed)           0.060     3.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr[5]
    SLICE_X59Y203        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.617     2.065    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/t_clk_i
    SLICE_X59Y203        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.521%)  route 0.060ns (60.480%))
  Logic Levels:           0  
  Clock Path Skew:        -1.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.070ns
    Source Clock Delay      (SCD):    3.244ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.504ns (routing 0.877ns, distribution 0.627ns)
  Clock Net Delay (Destination): 1.622ns (routing 0.870ns, distribution 0.752ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.504     3.244    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y231        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y231        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.283 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.060     3.342    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr[1]
    SLICE_X58Y231        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.622     2.070    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_clk_i
    SLICE_X58Y231        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.735%)  route 0.062ns (61.265%))
  Logic Levels:           0  
  Clock Path Skew:        -1.165ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.077ns
    Source Clock Delay      (SCD):    3.242ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.502ns (routing 0.877ns, distribution 0.625ns)
  Clock Net Delay (Destination): 1.629ns (routing 0.870ns, distribution 0.759ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.502     3.242    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X57Y199        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y199        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.281 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.062     3.342    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr[2]
    SLICE_X58Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.629     2.077    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/t_clk_i
    SLICE_X58Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.925%)  route 0.059ns (60.075%))
  Logic Levels:           0  
  Clock Path Skew:        -1.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.071ns
    Source Clock Delay      (SCD):    3.245ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.505ns (routing 0.877ns, distribution 0.628ns)
  Clock Net Delay (Destination): 1.623ns (routing 0.870ns, distribution 0.753ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.505     3.245    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y201        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y201        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     3.284 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/Q
                         net (fo=2, routed)           0.059     3.342    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr[4]
    SLICE_X58Y200        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.623     2.071    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/t_clk_i
    SLICE_X58Y200        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.109ns  (logic 0.040ns (36.673%)  route 0.069ns (63.327%))
  Logic Levels:           0  
  Clock Path Skew:        -1.172ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.062ns
    Source Clock Delay      (SCD):    3.234ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.494ns (routing 0.877ns, distribution 0.617ns)
  Clock Net Delay (Destination): 1.614ns (routing 0.870ns, distribution 0.744ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.494     3.234    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/c_clk_i
    SLICE_X58Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y207        FDCE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     3.274 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.069     3.343    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X57Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.614     2.062    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X57Y207        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.041ns (40.321%)  route 0.061ns (59.679%))
  Logic Levels:           0  
  Clock Path Skew:        -1.161ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.081ns
    Source Clock Delay      (SCD):    3.242ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.502ns (routing 0.877ns, distribution 0.625ns)
  Clock Net Delay (Destination): 1.633ns (routing 0.870ns, distribution 0.763ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.502     3.242    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X57Y199        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y199        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.283 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=2, routed)           0.061     3.343    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr[0]
    SLICE_X58Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.633     2.081    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/t_clk_i
    SLICE_X58Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.634%)  route 0.067ns (63.366%))
  Logic Levels:           0  
  Clock Path Skew:        -1.166ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.075ns
    Source Clock Delay      (SCD):    3.241ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.501ns (routing 0.877ns, distribution 0.624ns)
  Clock Net Delay (Destination): 1.627ns (routing 0.870ns, distribution 0.757ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.501     3.241    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/c_clk_i
    SLICE_X58Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y234        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.280 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.067     3.347    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X58Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.627     2.075    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X58Y236        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.615%)  route 0.065ns (62.385%))
  Logic Levels:           0  
  Clock Path Skew:        -1.162ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.082ns
    Source Clock Delay      (SCD):    3.244ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.504ns (routing 0.877ns, distribution 0.627ns)
  Clock Net Delay (Destination): 1.634ns (routing 0.870ns, distribution 0.764ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.504     3.244    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X57Y225        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y225        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.283 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/Q
                         net (fo=2, routed)           0.065     3.348    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr[3]
    SLICE_X57Y226        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.634     2.082    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/t_clk_i
    SLICE_X57Y226        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/wr_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.617%)  route 0.059ns (60.383%))
  Logic Levels:           0  
  Clock Path Skew:        -1.175ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.075ns
    Source Clock Delay      (SCD):    3.251ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.511ns (routing 0.877ns, distribution 0.634ns)
  Clock Net Delay (Destination): 1.627ns (routing 0.870ns, distribution 0.757ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.511     3.251    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y232        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y232        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.290 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/Q
                         net (fo=2, routed)           0.059     3.349    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr[8]
    SLICE_X58Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.627     2.075    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_clk_i
    SLICE_X58Y233        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/wr_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.038ns (37.371%)  route 0.064ns (62.629%))
  Logic Levels:           0  
  Clock Path Skew:        -1.173ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.075ns
    Source Clock Delay      (SCD):    3.248ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.508ns (routing 0.877ns, distribution 0.631ns)
  Clock Net Delay (Destination): 1.627ns (routing 0.870ns, distribution 0.757ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.508     3.248    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X56Y200        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y200        FDCE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     3.286 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                         net (fo=2, routed)           0.064     3.350    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr[7]
    SLICE_X56Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.627     2.075    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/t_clk_i
    SLICE_X56Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[7]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFDAC1_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.286ns  (logic 0.079ns (6.143%)  route 1.207ns (93.857%))
  Logic Levels:           0  
  Clock Path Skew:        0.442ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.230ns
    Source Clock Delay      (SCD):    2.788ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.562ns (routing 0.777ns, distribution 1.785ns)
  Clock Net Delay (Destination): 2.709ns (routing 1.313ns, distribution 1.396ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.562     2.788    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X108Y116       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y116       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.867 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           1.207     4.074    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X113Y238       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.126     0.407    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.709     3.230    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X113Y238       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.637ns  (logic 0.039ns (6.122%)  route 0.598ns (93.878%))
  Logic Levels:           0  
  Clock Path Skew:        0.775ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    1.524ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.404ns (routing 0.421ns, distribution 0.983ns)
  Clock Net Delay (Destination): 1.851ns (routing 0.870ns, distribution 0.981ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.404     1.524    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X108Y116       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y116       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.563 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           0.598     2.161    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X113Y238       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.142     0.366    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.448 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.851     2.299    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X113Y238       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.024ns  (logic 0.104ns (5.138%)  route 1.920ns (94.862%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.724ns (routing 1.417ns, distribution 1.307ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.695     1.695    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X55Y251        LUT1 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.104     1.799 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.225     2.024    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X55Y251        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.724     6.527    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X55Y251        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.978ns  (logic 0.033ns (3.375%)  route 0.945ns (96.625%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.870ns (routing 0.956ns, distribution 0.914ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.849     0.849    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X55Y251        LUT1 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.033     0.882 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.096     0.978    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X55Y251        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.870     3.841    d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X55Y251        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           177 Endpoints
Min Delay           177 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.583ns  (logic 0.078ns (13.372%)  route 0.505ns (86.628%))
  Logic Levels:           0  
  Clock Path Skew:        3.054ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.444ns
    Source Clock Delay      (SCD):    3.390ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.717ns (routing 1.446ns, distribution 1.271ns)
  Clock Net Delay (Destination): 2.641ns (routing 1.417ns, distribution 1.224ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.717     3.390    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X66Y214        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y214        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.468 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           0.505     3.973    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X79Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.641     6.444    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X79Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.335ns  (logic 0.078ns (23.284%)  route 0.257ns (76.716%))
  Logic Levels:           0  
  Clock Path Skew:        3.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.402ns
    Source Clock Delay      (SCD):    3.402ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.729ns (routing 1.446ns, distribution 1.283ns)
  Clock Net Delay (Destination): 2.599ns (routing 1.417ns, distribution 1.182ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.729     3.402    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X66Y203        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y203        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.480 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           0.257     3.737    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X66Y203        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.599     6.402    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X66Y203        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.289ns  (logic 0.078ns (26.971%)  route 0.211ns (73.029%))
  Logic Levels:           0  
  Clock Path Skew:        3.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.402ns
    Source Clock Delay      (SCD):    3.402ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.729ns (routing 1.446ns, distribution 1.283ns)
  Clock Net Delay (Destination): 2.599ns (routing 1.417ns, distribution 1.182ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.729     3.402    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X66Y203        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y203        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     3.480 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           0.211     3.691    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X66Y203        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.599     6.402    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X66Y203        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.311ns  (logic 0.132ns (10.067%)  route 1.179ns (89.933%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        3.136ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.430ns
    Source Clock Delay      (SCD):    3.294ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.621ns (routing 1.446ns, distribution 1.175ns)
  Clock Net Delay (Destination): 2.627ns (routing 1.417ns, distribution 1.210ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.621     3.294    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X58Y256        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y256        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     3.375 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/Q
                         net (fo=295, routed)         1.107     4.482    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[3]
    SLICE_X67Y236        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.051     4.533 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][2]_i_1/O
                         net (fo=1, routed)           0.072     4.605    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[2]
    SLICE_X67Y236        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.627     6.430    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X67Y236        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.290ns  (logic 0.081ns (6.281%)  route 1.209ns (93.719%))
  Logic Levels:           0  
  Clock Path Skew:        3.138ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.432ns
    Source Clock Delay      (SCD):    3.294ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.621ns (routing 1.446ns, distribution 1.175ns)
  Clock Net Delay (Destination): 2.629ns (routing 1.417ns, distribution 1.212ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.621     3.294    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X58Y256        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y256        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     3.375 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[3]/Q
                         net (fo=295, routed)         1.209     4.584    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[3]
    SLICE_X68Y239        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.629     6.432    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X68Y239        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.221ns  (logic 0.201ns (16.459%)  route 1.020ns (83.541%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        3.131ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.432ns
    Source Clock Delay      (SCD):    3.301ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.628ns (routing 1.446ns, distribution 1.182ns)
  Clock Net Delay (Destination): 2.629ns (routing 1.417ns, distribution 1.212ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.628     3.301    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X59Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y242        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.380 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=296, routed)         0.616     3.996    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[1]
    SLICE_X66Y239        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.122     4.118 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][0]_i_1/O
                         net (fo=2, routed)           0.404     4.522    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_reg[0][0]
    SLICE_X68Y239        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.629     6.432    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X68Y239        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.131ns  (logic 0.146ns (12.912%)  route 0.985ns (87.088%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        3.138ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.432ns
    Source Clock Delay      (SCD):    3.294ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.621ns (routing 1.446ns, distribution 1.175ns)
  Clock Net Delay (Destination): 2.629ns (routing 1.417ns, distribution 1.212ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.621     3.294    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X58Y256        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y256        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.374 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/Q
                         net (fo=296, routed)         0.731     4.105    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X66Y239        LUT2 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.066     4.171 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][1]_i_1/O
                         net (fo=1, routed)           0.254     4.425    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[1]
    SLICE_X68Y239        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.629     6.432    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X68Y239        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_126_139/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[131]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.894ns  (logic 0.307ns (34.340%)  route 0.587ns (65.660%))
  Logic Levels:           0  
  Clock Path Skew:        2.975ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.422ns
    Source Clock Delay      (SCD):    3.446ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.773ns (routing 1.446ns, distribution 1.327ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.417ns, distribution 1.202ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.773     3.446    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_126_139/WCLK
    SLICE_X66Y201        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_126_139/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y201        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     3.753 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_126_139/RAMC_D1/O
                         net (fo=1, routed)           0.587     4.340    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[131]
    SLICE_X67Y222        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[131]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.619     6.422    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X67Y222        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[131]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_154_167/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[154]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.854ns  (logic 0.289ns (33.841%)  route 0.565ns (66.159%))
  Logic Levels:           0  
  Clock Path Skew:        2.981ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.419ns
    Source Clock Delay      (SCD):    3.438ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.765ns (routing 1.446ns, distribution 1.319ns)
  Clock Net Delay (Destination): 2.616ns (routing 1.417ns, distribution 1.199ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.765     3.438    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_154_167/WCLK
    SLICE_X66Y198        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_154_167/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y198        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     3.727 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_154_167/RAMA/O
                         net (fo=1, routed)           0.565     4.292    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[154]
    SLICE_X66Y233        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[154]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.616     6.419    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X66Y233        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[154]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_126_139/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[133]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.822ns  (logic 0.301ns (36.618%)  route 0.521ns (63.382%))
  Logic Levels:           0  
  Clock Path Skew:        2.975ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.422ns
    Source Clock Delay      (SCD):    3.446ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.773ns (routing 1.446ns, distribution 1.327ns)
  Clock Net Delay (Destination): 2.619ns (routing 1.417ns, distribution 1.202ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.773     3.446    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_126_139/WCLK
    SLICE_X66Y201        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_126_139/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y201        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     3.747 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_126_139/RAMD_D1/O
                         net (fo=1, routed)           0.521     4.268    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[133]
    SLICE_X67Y222        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[133]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.619     6.422    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X67Y222        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[133]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.115ns  (logic 0.038ns (33.073%)  route 0.077ns (66.927%))
  Logic Levels:           0  
  Clock Path Skew:        1.918ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.756ns
    Source Clock Delay      (SCD):    1.838ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.489ns (routing 0.779ns, distribution 0.710ns)
  Clock Net Delay (Destination): 1.785ns (routing 0.956ns, distribution 0.829ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.489     1.838    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X66Y203        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y203        FDCE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.876 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[11]/Q
                         net (fo=2, routed)           0.077     1.953    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X66Y203        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.785     3.756    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X66Y203        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.039ns (28.467%)  route 0.098ns (71.533%))
  Logic Levels:           0  
  Clock Path Skew:        1.918ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.756ns
    Source Clock Delay      (SCD):    1.838ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.489ns (routing 0.779ns, distribution 0.710ns)
  Clock Net Delay (Destination): 1.785ns (routing 0.956ns, distribution 0.829ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.489     1.838    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X66Y203        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y203        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.877 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[10]/Q
                         net (fo=2, routed)           0.098     1.975    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X66Y203        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.785     3.756    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X66Y203        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.275ns  (logic 0.039ns (14.177%)  route 0.236ns (85.823%))
  Logic Levels:           0  
  Clock Path Skew:        1.951ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.783ns
    Source Clock Delay      (SCD):    1.832ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.483ns (routing 0.779ns, distribution 0.704ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.956ns, distribution 0.856ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.483     1.832    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X66Y214        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y214        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.871 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[8]/Q
                         net (fo=2, routed)           0.236     2.107    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X79Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.812     3.783    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X79Y217        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[179]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.189ns  (logic 0.111ns (58.730%)  route 0.078ns (41.270%))
  Logic Levels:           0  
  Clock Path Skew:        1.952ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.793ns
    Source Clock Delay      (SCD):    1.842ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.493ns (routing 0.779ns, distribution 0.714ns)
  Clock Net Delay (Destination): 1.822ns (routing 0.956ns, distribution 0.866ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.493     1.842    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/WCLK
    SLICE_X63Y255        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y255        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     1.953 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF_D1/O
                         net (fo=1, routed)           0.078     2.031    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[179]
    SLICE_X64Y254        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[179]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.822     3.793    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X64Y254        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[179]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_42_55/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[53]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.187ns  (logic 0.111ns (59.358%)  route 0.076ns (40.642%))
  Logic Levels:           0  
  Clock Path Skew:        1.951ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.794ns
    Source Clock Delay      (SCD):    1.844ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.495ns (routing 0.779ns, distribution 0.716ns)
  Clock Net Delay (Destination): 1.823ns (routing 0.956ns, distribution 0.867ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.495     1.844    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_42_55/WCLK
    SLICE_X63Y251        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_42_55/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y251        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     1.955 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_42_55/RAMF_D1/O
                         net (fo=1, routed)           0.076     2.031    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[53]
    SLICE_X64Y252        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[53]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.823     3.794    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X64Y252        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[53]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.188ns  (logic 0.111ns (59.043%)  route 0.077ns (40.957%))
  Logic Levels:           0  
  Clock Path Skew:        1.947ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.790ns
    Source Clock Delay      (SCD):    1.843ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.494ns (routing 0.779ns, distribution 0.715ns)
  Clock Net Delay (Destination): 1.819ns (routing 0.956ns, distribution 0.863ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.494     1.843    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/WCLK
    SLICE_X66Y265        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y265        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     1.954 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMA_D1/O
                         net (fo=1, routed)           0.077     2.031    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[1]
    SLICE_X66Y263        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.819     3.790    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X66Y263        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_280_293/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[291]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.199ns  (logic 0.111ns (55.779%)  route 0.088ns (44.221%))
  Logic Levels:           0  
  Clock Path Skew:        1.949ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.785ns
    Source Clock Delay      (SCD):    1.836ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.487ns (routing 0.779ns, distribution 0.708ns)
  Clock Net Delay (Destination): 1.814ns (routing 0.956ns, distribution 0.858ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.487     1.836    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_280_293/WCLK
    SLICE_X63Y259        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_280_293/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y259        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     1.947 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_280_293/RAMF_D1/O
                         net (fo=1, routed)           0.088     2.035    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[291]
    SLICE_X64Y255        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[291]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.814     3.785    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X64Y255        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[291]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.194ns  (logic 0.111ns (57.216%)  route 0.083ns (42.783%))
  Logic Levels:           0  
  Clock Path Skew:        1.947ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.790ns
    Source Clock Delay      (SCD):    1.843ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.494ns (routing 0.779ns, distribution 0.715ns)
  Clock Net Delay (Destination): 1.819ns (routing 0.956ns, distribution 0.863ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.494     1.843    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/WCLK
    SLICE_X66Y265        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y265        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     1.954 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_0_13/RAMF_D1/O
                         net (fo=1, routed)           0.083     2.037    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[11]
    SLICE_X66Y263        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.819     3.790    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X66Y263        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_14_27/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.206ns  (logic 0.108ns (52.427%)  route 0.098ns (47.573%))
  Logic Levels:           0  
  Clock Path Skew:        1.947ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.781ns
    Source Clock Delay      (SCD):    1.834ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.485ns (routing 0.779ns, distribution 0.706ns)
  Clock Net Delay (Destination): 1.810ns (routing 0.956ns, distribution 0.854ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.485     1.834    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_14_27/WCLK
    SLICE_X63Y263        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_14_27/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y263        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     1.942 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_14_27/RAME/O
                         net (fo=1, routed)           0.098     2.040    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[22]
    SLICE_X64Y261        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.810     3.781    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X64Y261        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[22]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_14_27/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.209ns  (logic 0.105ns (50.239%)  route 0.104ns (49.761%))
  Logic Levels:           0  
  Clock Path Skew:        1.947ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.781ns
    Source Clock Delay      (SCD):    1.834ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.128ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.485ns (routing 0.779ns, distribution 0.706ns)
  Clock Net Delay (Destination): 1.810ns (routing 0.956ns, distribution 0.854ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.485     1.834    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_14_27/WCLK
    SLICE_X63Y263        RAMD32                                       r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_14_27/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y263        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     1.939 r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_14_27/RAMG_D1/O
                         net (fo=1, routed)           0.104     2.043    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[27]
    SLICE_X64Y261        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.810     3.781    d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X64Y261        FDRE                                         r  d_1_i/axis_cdcsync_v1_0/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[27]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay           427 Endpoints
Min Delay           427 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.001ns  (logic 0.079ns (7.894%)  route 0.922ns (92.106%))
  Logic Levels:           0  
  Clock Path Skew:        3.858ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.478ns
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.394ns (routing 0.777ns, distribution 1.617ns)
  Clock Net Delay (Destination): 2.675ns (routing 1.417ns, distribution 1.258ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.394     2.620    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X85Y95         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y95         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.699 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.922     3.621    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X76Y113        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.675     6.478    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X76Y113        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.939ns  (logic 0.076ns (8.095%)  route 0.863ns (91.905%))
  Logic Levels:           0  
  Clock Path Skew:        3.911ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.436ns
    Source Clock Delay      (SCD):    2.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.299ns (routing 0.777ns, distribution 1.522ns)
  Clock Net Delay (Destination): 2.633ns (routing 1.417ns, distribution 1.216ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.299     2.525    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X79Y136        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y136        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.601 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.863     3.464    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X79Y208        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.633     6.436    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X79Y208        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.525ns  (logic 0.079ns (15.048%)  route 0.446ns (84.952%))
  Logic Levels:           0  
  Clock Path Skew:        3.878ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.674ns
    Source Clock Delay      (SCD):    2.796ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.570ns (routing 0.777ns, distribution 1.793ns)
  Clock Net Delay (Destination): 2.871ns (routing 1.417ns, distribution 1.454ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.570     2.796    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X113Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y98        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.875 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/Q
                         net (fo=1, routed)           0.446     3.321    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/src_in
    SLICE_X108Y87        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.871     6.674    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/dest_clk
    SLICE_X108Y87        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.877ns  (logic 0.218ns (7.576%)  route 2.659ns (92.424%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        4.071ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.571ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.417ns, distribution 1.351ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X67Y161        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y161        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.577 r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.807     4.384    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X80Y131        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.141     4.525 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=9, routed)           0.852     5.377    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in__0[1]
    SLICE_X84Y115        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.768     6.571    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X84Y115        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_2/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.853ns  (logic 0.218ns (7.642%)  route 2.635ns (92.358%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        4.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.563ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.760ns (routing 1.417ns, distribution 1.343ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X67Y161        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y161        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.577 r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.807     4.384    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X80Y131        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.141     4.525 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=9, routed)           0.828     5.353    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in__0[1]
    SLICE_X81Y110        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_2/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.760     6.563    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X81Y110        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_2/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_5/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.831ns  (logic 0.218ns (7.701%)  route 2.613ns (92.299%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        4.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.563ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.760ns (routing 1.417ns, distribution 1.343ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X67Y161        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y161        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.577 r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.807     4.384    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X80Y131        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.141     4.525 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=9, routed)           0.806     5.331    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in__0[1]
    SLICE_X81Y110        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_5/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.760     6.563    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X81Y110        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_5/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_3/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.777ns  (logic 0.218ns (7.852%)  route 2.559ns (92.148%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        4.065ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.565ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.762ns (routing 1.417ns, distribution 1.345ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X67Y161        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y161        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.577 r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.807     4.384    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X80Y131        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.141     4.525 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=9, routed)           0.751     5.276    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in__0[1]
    SLICE_X84Y133        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_3/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.762     6.565    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X84Y133        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_3/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_4/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.739ns  (logic 0.218ns (7.960%)  route 2.521ns (92.040%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        4.068ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.568ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.765ns (routing 1.417ns, distribution 1.348ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X67Y161        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y161        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.577 r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.807     4.384    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X80Y131        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.141     4.525 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=9, routed)           0.713     5.238    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in__0[1]
    SLICE_X84Y131        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_4/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.765     6.568    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X84Y131        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_4/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_1/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.596ns  (logic 0.218ns (8.398%)  route 2.378ns (91.602%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        4.047ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.547ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.744ns (routing 1.417ns, distribution 1.327ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X67Y161        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y161        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.577 r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.807     4.384    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X80Y131        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.141     4.525 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=9, routed)           0.571     5.096    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in__0[1]
    SLICE_X81Y133        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_1/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.744     6.547    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X81Y133        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_1/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_7/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.381ns  (logic 0.218ns (9.157%)  route 2.163ns (90.843%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        3.974ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.474ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.671ns (routing 1.417ns, distribution 1.254ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X67Y161        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y161        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.577 r  d_1_i/axis_weighted_buffer_0/inst/axi_slv_i/slv_reg1_reg[1]/Q
                         net (fo=2, routed)           1.807     4.384    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[13]_15[1]
    SLICE_X80Y131        LUT4 (Prop_B5LUT_SLICEL_I0_O)
                                                      0.141     4.525 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r[1]_i_1/O
                         net (fo=9, routed)           0.356     4.881    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/p_0_in__0[1]
    SLICE_X80Y131        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_7/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.671     6.474    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X80Y131        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[1]_replica_7/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.038ns (30.159%)  route 0.088ns (69.841%))
  Logic Levels:           0  
  Clock Path Skew:        2.426ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.818ns
    Source Clock Delay      (SCD):    1.392ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.272ns (routing 0.421ns, distribution 0.851ns)
  Clock Net Delay (Destination): 1.847ns (routing 0.956ns, distribution 0.891ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.272     1.392    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X76Y113        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y113        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.430 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/Q
                         net (fo=1, routed)           0.088     1.518    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[4]
    SLICE_X76Y114        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.847     3.818    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X76Y114        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.166ns  (logic 0.039ns (23.494%)  route 0.127ns (76.506%))
  Logic Levels:           0  
  Clock Path Skew:        2.426ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.818ns
    Source Clock Delay      (SCD):    1.392ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.272ns (routing 0.421ns, distribution 0.851ns)
  Clock Net Delay (Destination): 1.847ns (routing 0.956ns, distribution 0.891ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.272     1.392    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X76Y118        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y118        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.431 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.127     1.558    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X76Y114        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.847     3.818    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X76Y114        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.203ns  (logic 0.038ns (18.719%)  route 0.165ns (81.281%))
  Logic Levels:           0  
  Clock Path Skew:        2.415ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.800ns
    Source Clock Delay      (SCD):    1.385ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.265ns (routing 0.421ns, distribution 0.844ns)
  Clock Net Delay (Destination): 1.829ns (routing 0.956ns, distribution 0.873ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.265     1.385    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y118        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y118        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.423 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.165     1.588    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X75Y127        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.829     3.800    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X75Y127        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.207ns  (logic 0.039ns (18.841%)  route 0.168ns (81.159%))
  Logic Levels:           0  
  Clock Path Skew:        2.413ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.798ns
    Source Clock Delay      (SCD):    1.385ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.265ns (routing 0.421ns, distribution 0.844ns)
  Clock Net Delay (Destination): 1.827ns (routing 0.956ns, distribution 0.871ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.265     1.385    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y117        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y117        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.424 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.168     1.592    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X75Y135        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.827     3.798    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X75Y135        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.230ns  (logic 0.039ns (16.957%)  route 0.191ns (83.043%))
  Logic Levels:           0  
  Clock Path Skew:        2.413ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.798ns
    Source Clock Delay      (SCD):    1.385ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.265ns (routing 0.421ns, distribution 0.844ns)
  Clock Net Delay (Destination): 1.827ns (routing 0.956ns, distribution 0.871ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.265     1.385    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X75Y118        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X75Y118        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.424 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.191     1.615    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X75Y135        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.827     3.798    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X75Y135        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.348ns  (logic 0.039ns (11.207%)  route 0.309ns (88.793%))
  Logic Levels:           0  
  Clock Path Skew:        2.412ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.779ns
    Source Clock Delay      (SCD):    1.367ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.247ns (routing 0.421ns, distribution 0.826ns)
  Clock Net Delay (Destination): 1.808ns (routing 0.956ns, distribution 0.852ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.247     1.367    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X80Y158        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y158        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.406 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.309     1.715    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X80Y214        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.808     3.779    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X80Y214        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.248ns  (logic 0.039ns (15.726%)  route 0.209ns (84.274%))
  Logic Levels:           0  
  Clock Path Skew:        2.420ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.949ns
    Source Clock Delay      (SCD):    1.529ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.409ns (routing 0.421ns, distribution 0.988ns)
  Clock Net Delay (Destination): 1.978ns (routing 0.956ns, distribution 1.022ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.409     1.529    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X113Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y98        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.568 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_done_i_reg/Q
                         net (fo=1, routed)           0.209     1.777    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/src_in
    SLICE_X108Y87        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.978     3.949    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/dest_clk
    SLICE_X108Y87        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.458ns  (logic 0.038ns (8.294%)  route 0.420ns (91.706%))
  Logic Levels:           0  
  Clock Path Skew:        2.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.777ns
    Source Clock Delay      (SCD):    1.378ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.258ns (routing 0.421ns, distribution 0.837ns)
  Clock Net Delay (Destination): 1.806ns (routing 0.956ns, distribution 0.850ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.258     1.378    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X79Y136        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y136        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.416 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.420     1.836    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X79Y208        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.806     3.777    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X79Y208        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.491ns  (logic 0.039ns (7.949%)  route 0.452ns (92.051%))
  Logic Levels:           0  
  Clock Path Skew:        2.384ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.818ns
    Source Clock Delay      (SCD):    1.434ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.314ns (routing 0.421ns, distribution 0.893ns)
  Clock Net Delay (Destination): 1.847ns (routing 0.956ns, distribution 0.891ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.314     1.434    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X85Y95         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y95         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.473 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.452     1.925    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X76Y113        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.847     3.818    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X76Y113        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.564ns  (logic 0.039ns (6.915%)  route 0.525ns (93.085%))
  Logic Levels:           0  
  Clock Path Skew:        2.465ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.832ns
    Source Clock Delay      (SCD):    1.367ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.247ns (routing 0.421ns, distribution 0.826ns)
  Clock Net Delay (Destination): 1.861ns (routing 0.956ns, distribution 0.905ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.247     1.367    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X80Y158        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y158        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.406 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.525     1.931    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X82Y210        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.861     3.832    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X82Y210        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.680ns  (logic 0.226ns (13.449%)  route 1.454ns (86.551%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        2.392ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.571ns
    Source Clock Delay      (SCD):    4.179ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.983ns (routing 0.696ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.417ns, distribution 1.351ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.983     4.179    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X78Y181        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y181        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.255 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           1.307     5.562    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X85Y121        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     5.712 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.147     5.859    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X85Y121        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.768     6.571    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X85Y121        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.411ns  (logic 0.078ns (18.978%)  route 0.333ns (81.022%))
  Logic Levels:           0  
  Clock Path Skew:        2.479ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.588ns
    Source Clock Delay      (SCD):    4.109ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.913ns (routing 0.696ns, distribution 1.217ns)
  Clock Net Delay (Destination): 2.785ns (routing 1.417ns, distribution 1.368ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.913     4.109    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X89Y121        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y121        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.187 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=1, routed)           0.333     4.520    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X87Y124        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.785     6.588    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X87Y124        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.472ns  (logic 0.079ns (16.737%)  route 0.393ns (83.263%))
  Logic Levels:           0  
  Clock Path Skew:        2.477ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.587ns
    Source Clock Delay      (SCD):    4.110ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.914ns (routing 0.696ns, distribution 1.218ns)
  Clock Net Delay (Destination): 2.784ns (routing 1.417ns, distribution 1.367ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.914     4.110    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X92Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y103        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     4.189 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.393     4.582    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X91Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.784     6.587    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X91Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.362ns  (logic 0.080ns (22.099%)  route 0.282ns (77.901%))
  Logic Levels:           0  
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.589ns
    Source Clock Delay      (SCD):    4.116ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.920ns (routing 0.696ns, distribution 1.224ns)
  Clock Net Delay (Destination): 2.786ns (routing 1.417ns, distribution 1.369ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.920     4.116    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y102        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     4.196 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.282     4.478    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.786     6.589    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.353ns  (logic 0.078ns (22.096%)  route 0.275ns (77.904%))
  Logic Levels:           0  
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.589ns
    Source Clock Delay      (SCD):    4.116ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.920ns (routing 0.696ns, distribution 1.224ns)
  Clock Net Delay (Destination): 2.786ns (routing 1.417ns, distribution 1.369ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.920     4.116    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y102        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.194 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.275     4.469    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.786     6.589    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.280ns  (logic 0.079ns (28.214%)  route 0.201ns (71.786%))
  Logic Levels:           0  
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.587ns
    Source Clock Delay      (SCD):    4.114ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.918ns (routing 0.696ns, distribution 1.222ns)
  Clock Net Delay (Destination): 2.784ns (routing 1.417ns, distribution 1.367ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.918     4.114    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X92Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y102        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.193 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.201     4.394    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X91Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.784     6.587    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X91Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.283ns  (logic 0.081ns (28.622%)  route 0.202ns (71.378%))
  Logic Levels:           0  
  Clock Path Skew:        2.481ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    6.591ns
    Source Clock Delay      (SCD):    4.110ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.914ns (routing 0.696ns, distribution 1.218ns)
  Clock Net Delay (Destination): 2.788ns (routing 1.417ns, distribution 1.371ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.914     4.110    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X92Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y103        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     4.191 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.202     4.393    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X92Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.788     6.591    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X92Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.231%)  route 0.082ns (67.769%))
  Logic Levels:           0  
  Clock Path Skew:        1.279ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.891ns
    Source Clock Delay      (SCD):    2.612ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.065ns (routing 0.385ns, distribution 0.680ns)
  Clock Net Delay (Destination): 1.920ns (routing 0.956ns, distribution 0.964ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.065     2.612    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X92Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y102        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.651 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.082     2.733    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X91Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.920     3.891    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X91Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.041ns (32.800%)  route 0.084ns (67.200%))
  Logic Levels:           0  
  Clock Path Skew:        1.284ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.893ns
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.062ns (routing 0.385ns, distribution 0.677ns)
  Clock Net Delay (Destination): 1.922ns (routing 0.956ns, distribution 0.966ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.062     2.609    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X92Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y103        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.650 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.084     2.734    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X92Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.922     3.893    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X92Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.154ns  (logic 0.039ns (25.325%)  route 0.115ns (74.675%))
  Logic Levels:           0  
  Clock Path Skew:        1.280ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.893ns
    Source Clock Delay      (SCD):    2.613ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.066ns (routing 0.385ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.922ns (routing 0.956ns, distribution 0.966ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.066     2.613    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y102        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.652 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.115     2.767    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.922     3.893    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.041ns (26.115%)  route 0.116ns (73.885%))
  Logic Levels:           0  
  Clock Path Skew:        1.280ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.893ns
    Source Clock Delay      (SCD):    2.613ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.066ns (routing 0.385ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.922ns (routing 0.956ns, distribution 0.966ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.066     2.613    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y102        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.654 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.116     2.770    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.922     3.893    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X93Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.179ns  (logic 0.039ns (21.788%)  route 0.140ns (78.212%))
  Logic Levels:           0  
  Clock Path Skew:        1.284ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.886ns
    Source Clock Delay      (SCD):    2.603ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.056ns (routing 0.385ns, distribution 0.671ns)
  Clock Net Delay (Destination): 1.915ns (routing 0.956ns, distribution 0.959ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.056     2.603    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X89Y121        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y121        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.642 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=1, routed)           0.140     2.782    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X87Y124        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.915     3.886    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X87Y124        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.219ns  (logic 0.039ns (17.808%)  route 0.180ns (82.192%))
  Logic Levels:           0  
  Clock Path Skew:        1.282ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.891ns
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.062ns (routing 0.385ns, distribution 0.677ns)
  Clock Net Delay (Destination): 1.920ns (routing 0.956ns, distribution 0.964ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.062     2.609    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X92Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y103        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.648 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.180     2.828    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X91Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.920     3.891    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X91Y102        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.829ns  (logic 0.098ns (11.816%)  route 0.731ns (88.184%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        1.229ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.871ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.095ns (routing 0.385ns, distribution 0.710ns)
  Clock Net Delay (Destination): 1.900ns (routing 0.956ns, distribution 0.944ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.095     2.642    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X78Y181        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y181        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.680 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.683     3.363    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X85Y121        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.060     3.423 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.048     3.471    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X85Y121        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.900     3.871    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X85Y121        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.179ns  (logic 0.096ns (4.406%)  route 2.083ns (95.594%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.497ns (routing 1.464ns, distribution 1.033ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           1.929     1.929    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X52Y258        LUT1 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     2.025 r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.154     2.179    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X52Y258        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.497     5.570    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X52Y258        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.060ns  (logic 0.040ns (3.775%)  route 1.020ns (96.225%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.714ns (routing 0.978ns, distribution 0.736ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=5, routed)           0.970     0.970    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X52Y258        LUT1 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.010 r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.050     1.060    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X52Y258        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.714     3.121    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X52Y258        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           203 Endpoints
Min Delay           203 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.022ns  (logic 0.079ns (7.730%)  route 0.943ns (92.270%))
  Logic Levels:           0  
  Clock Path Skew:        2.233ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.541ns
    Source Clock Delay      (SCD):    3.307ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.634ns (routing 1.446ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.464ns, distribution 1.004ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.634     3.307    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X57Y240        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y240        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.386 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=3, routed)           0.943     4.329    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/rd_gptr[2]
    SLICE_X59Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.468     5.541    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X59Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.012ns  (logic 0.079ns (7.806%)  route 0.933ns (92.194%))
  Logic Levels:           0  
  Clock Path Skew:        2.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.387ns
    Source Clock Delay      (SCD):    3.294ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.621ns (routing 1.446ns, distribution 1.175ns)
  Clock Net Delay (Destination): 2.314ns (routing 1.464ns, distribution 0.850ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.621     3.294    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X50Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y216        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     3.373 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[0]/Q
                         net (fo=1, routed)           0.933     4.306    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[0]
    SLICE_X36Y210        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.314     5.387    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X36Y210        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.756ns  (logic 0.078ns (10.315%)  route 0.678ns (89.686%))
  Logic Levels:           0  
  Clock Path Skew:        2.191ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.623ns
    Source Clock Delay      (SCD):    3.431ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.758ns (routing 1.446ns, distribution 1.312ns)
  Clock Net Delay (Destination): 2.550ns (routing 1.464ns, distribution 1.086ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.758     3.431    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y300        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.509 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=3, routed)           0.678     4.188    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr[8]
    SLICE_X62Y289        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.550     5.623    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X62Y289        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.741ns  (logic 0.076ns (10.253%)  route 0.665ns (89.747%))
  Logic Levels:           0  
  Clock Path Skew:        2.192ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.623ns
    Source Clock Delay      (SCD):    3.430ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.757ns (routing 1.446ns, distribution 1.311ns)
  Clock Net Delay (Destination): 2.550ns (routing 1.464ns, distribution 1.086ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.757     3.430    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X63Y300        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y300        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     3.506 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=3, routed)           0.665     4.172    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr[7]
    SLICE_X62Y289        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.550     5.623    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/c_clk_i
    SLICE_X62Y289        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/rd_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.729ns  (logic 0.079ns (10.837%)  route 0.650ns (89.163%))
  Logic Levels:           0  
  Clock Path Skew:        2.169ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.525ns
    Source Clock Delay      (SCD):    3.356ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.683ns (routing 1.446ns, distribution 1.237ns)
  Clock Net Delay (Destination): 2.452ns (routing 1.464ns, distribution 0.988ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.683     3.356    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X62Y213        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y213        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.435 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=3, routed)           0.650     4.085    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr[2]
    SLICE_X58Y211        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.452     5.525    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/c_clk_i
    SLICE_X58Y211        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[8].trig_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.734ns  (logic 0.079ns (10.757%)  route 0.655ns (89.243%))
  Logic Levels:           0  
  Clock Path Skew:        2.196ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.541ns
    Source Clock Delay      (SCD):    3.345ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.672ns (routing 1.446ns, distribution 1.226ns)
  Clock Net Delay (Destination): 2.468ns (routing 1.464ns, distribution 1.004ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.672     3.345    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X58Y239        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y239        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.424 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=3, routed)           0.655     4.079    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/rd_gptr[5]
    SLICE_X58Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.468     5.541    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X58Y238        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/rd_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.666ns  (logic 0.079ns (11.869%)  route 0.587ns (88.131%))
  Logic Levels:           0  
  Clock Path Skew:        2.184ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.595ns
    Source Clock Delay      (SCD):    3.411ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.738ns (routing 1.446ns, distribution 1.292ns)
  Clock Net Delay (Destination): 2.522ns (routing 1.464ns, distribution 1.058ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.738     3.411    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X65Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y192        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.490 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/Q
                         net (fo=3, routed)           0.587     4.077    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr[3]
    SLICE_X63Y194        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.522     5.595    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/c_clk_i
    SLICE_X63Y194        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.738ns  (logic 0.081ns (10.977%)  route 0.657ns (89.023%))
  Logic Levels:           0  
  Clock Path Skew:        2.263ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.563ns
    Source Clock Delay      (SCD):    3.299ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.626ns (routing 1.446ns, distribution 1.180ns)
  Clock Net Delay (Destination): 2.490ns (routing 1.464ns, distribution 1.026ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.626     3.299    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X58Y281        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y281        FDCE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     3.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=5, routed)           0.657     4.037    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr[0]
    SLICE_X59Y274        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.490     5.563    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/c_clk_i
    SLICE_X59Y274        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.589ns  (logic 0.079ns (13.420%)  route 0.510ns (86.580%))
  Logic Levels:           0  
  Clock Path Skew:        2.188ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.594ns
    Source Clock Delay      (SCD):    3.406ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.733ns (routing 1.446ns, distribution 1.287ns)
  Clock Net Delay (Destination): 2.521ns (routing 1.464ns, distribution 1.057ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.733     3.406    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X65Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y192        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.485 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=3, routed)           0.510     3.995    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr[8]
    SLICE_X63Y196        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.521     5.594    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/c_clk_i
    SLICE_X63Y196        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.541ns  (logic 0.078ns (14.412%)  route 0.463ns (85.588%))
  Logic Levels:           0  
  Clock Path Skew:        2.160ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.584ns
    Source Clock Delay      (SCD):    3.423ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.750ns (routing 1.446ns, distribution 1.304ns)
  Clock Net Delay (Destination): 2.511ns (routing 1.464ns, distribution 1.047ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.750     3.423    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X66Y192        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y192        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=3, routed)           0.463     3.965    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr[7]
    SLICE_X63Y197        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.511     5.584    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/c_clk_i
    SLICE_X63Y197        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/rd_gptr_cdc_reg[7]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.500%)  route 0.065ns (62.500%))
  Logic Levels:           0  
  Clock Path Skew:        1.316ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.092ns
    Source Clock Delay      (SCD):    1.776ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.427ns (routing 0.779ns, distribution 0.648ns)
  Clock Net Delay (Destination): 1.685ns (routing 0.978ns, distribution 0.707ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.427     1.776    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X47Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y218        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.815 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[23]/Q
                         net (fo=1, routed)           0.065     1.880    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[23]
    SLICE_X47Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.685     3.092    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X47Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[23]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.500%)  route 0.065ns (62.500%))
  Logic Levels:           0  
  Clock Path Skew:        1.308ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.085ns
    Source Clock Delay      (SCD):    1.777ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.428ns (routing 0.779ns, distribution 0.649ns)
  Clock Net Delay (Destination): 1.678ns (routing 0.978ns, distribution 0.700ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.428     1.777    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X49Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y218        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.816 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[28]/Q
                         net (fo=1, routed)           0.065     1.881    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[28]
    SLICE_X49Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.678     3.085    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X49Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.394%)  route 0.060ns (60.606%))
  Logic Levels:           0  
  Clock Path Skew:        1.298ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.083ns
    Source Clock Delay      (SCD):    1.785ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.436ns (routing 0.779ns, distribution 0.657ns)
  Clock Net Delay (Destination): 1.676ns (routing 0.978ns, distribution 0.698ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.436     1.785    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X47Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y216        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.824 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[6]/Q
                         net (fo=1, routed)           0.060     1.884    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[6]
    SLICE_X47Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.676     3.083    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X47Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.700%)  route 0.062ns (61.300%))
  Logic Levels:           0  
  Clock Path Skew:        1.305ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.090ns
    Source Clock Delay      (SCD):    1.786ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.437ns (routing 0.779ns, distribution 0.658ns)
  Clock Net Delay (Destination): 1.683ns (routing 0.978ns, distribution 0.705ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.437     1.786    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X58Y206        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y206        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.825 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=3, routed)           0.062     1.886    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr[1]
    SLICE_X57Y206        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.683     3.090    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/c_clk_i
    SLICE_X57Y206        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.041ns (39.375%)  route 0.063ns (60.625%))
  Logic Levels:           0  
  Clock Path Skew:        1.309ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.094ns
    Source Clock Delay      (SCD):    1.786ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.437ns (routing 0.779ns, distribution 0.658ns)
  Clock Net Delay (Destination): 1.687ns (routing 0.978ns, distribution 0.709ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.437     1.786    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X58Y206        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y206        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.827 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=3, routed)           0.063     1.890    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr[0]
    SLICE_X57Y206        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.687     3.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/c_clk_i
    SLICE_X57Y206        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.099%)  route 0.063ns (61.901%))
  Logic Levels:           0  
  Clock Path Skew:        1.307ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.097ns
    Source Clock Delay      (SCD):    1.791ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.442ns (routing 0.779ns, distribution 0.663ns)
  Clock Net Delay (Destination): 1.690ns (routing 0.978ns, distribution 0.712ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.442     1.791    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X55Y226        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y226        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.830 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=3, routed)           0.063     1.893    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr[8]
    SLICE_X55Y225        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.690     3.097    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X55Y225        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.088%)  route 0.066ns (62.912%))
  Logic Levels:           0  
  Clock Path Skew:        1.303ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.093ns
    Source Clock Delay      (SCD):    1.791ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.442ns (routing 0.779ns, distribution 0.663ns)
  Clock Net Delay (Destination): 1.686ns (routing 0.978ns, distribution 0.708ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.442     1.791    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X55Y226        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y226        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.830 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=3, routed)           0.066     1.896    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr[5]
    SLICE_X55Y224        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.686     3.093    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X55Y224        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.099%)  route 0.063ns (61.901%))
  Logic Levels:           0  
  Clock Path Skew:        1.304ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.097ns
    Source Clock Delay      (SCD):    1.794ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.445ns (routing 0.779ns, distribution 0.666ns)
  Clock Net Delay (Destination): 1.690ns (routing 0.978ns, distribution 0.712ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.445     1.794    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X55Y226        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y226        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.833 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/Q
                         net (fo=3, routed)           0.063     1.896    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr[6]
    SLICE_X55Y225        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.690     3.097    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/c_clk_i
    SLICE_X55Y225        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[9].trig_fifo_inst/rd_gptr_cdc_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        1.298ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.083ns
    Source Clock Delay      (SCD):    1.785ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.436ns (routing 0.779ns, distribution 0.657ns)
  Clock Net Delay (Destination): 1.676ns (routing 0.978ns, distribution 0.698ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.436     1.785    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_clk_i
    SLICE_X47Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y216        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.825 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.t_time_abs_cdc_reg[2]/Q
                         net (fo=1, routed)           0.078     1.903    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/t_time_abs_cdc[2]
    SLICE_X47Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.676     3.083    d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/c_clk_i
    SLICE_X47Y216        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_CTRL/QPER_TIME_READ.c_time_abs_r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.368%)  route 0.065ns (62.631%))
  Logic Levels:           0  
  Clock Path Skew:        1.300ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.099ns
    Source Clock Delay      (SCD):    1.800ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.451ns (routing 0.779ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.692ns (routing 0.978ns, distribution 0.714ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.451     1.800    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X59Y199        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y199        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.839 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=3, routed)           0.065     1.904    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr[4]
    SLICE_X57Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.692     3.099    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/c_clk_i
    SLICE_X57Y199        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/rd_gptr_cdc_reg[4]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           354 Endpoints
Min Delay           354 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[57]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.969ns  (logic 0.305ns (31.476%)  route 0.664ns (68.524%))
  Logic Levels:           0  
  Clock Path Skew:        3.096ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.595ns
    Source Clock Delay      (SCD):    2.499ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.273ns (routing 0.777ns, distribution 1.496ns)
  Clock Net Delay (Destination): 2.522ns (routing 1.464ns, distribution 1.058ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.273     2.499    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/WCLK
    SLICE_X67Y185        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y185        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     2.804 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMA_D1/O
                         net (fo=1, routed)           0.664     3.468    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[57]
    SLICE_X63Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[57]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.522     5.595    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X63Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[57]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[32]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.964ns  (logic 0.288ns (29.876%)  route 0.676ns (70.124%))
  Logic Levels:           0  
  Clock Path Skew:        3.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.535ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.462ns (routing 1.464ns, distribution 0.998ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X67Y183        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y183        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     2.788 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC/O
                         net (fo=1, routed)           0.676     3.464    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[32]
    SLICE_X58Y192        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[32]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.462     5.535    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X58Y192        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[32]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.954ns  (logic 0.292ns (30.608%)  route 0.662ns (69.392%))
  Logic Levels:           0  
  Clock Path Skew:        3.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.582ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.509ns (routing 1.464ns, distribution 1.045ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X67Y183        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y183        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     2.792 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/O
                         net (fo=1, routed)           0.662     3.454    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[30]
    SLICE_X61Y186        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.509     5.582    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X61Y186        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[30]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.953ns  (logic 0.304ns (31.899%)  route 0.649ns (68.101%))
  Logic Levels:           0  
  Clock Path Skew:        3.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.537ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.464ns (routing 1.464ns, distribution 1.000ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X67Y183        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y183        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     2.804 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/O
                         net (fo=1, routed)           0.649     3.453    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[39]
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.464     5.537    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[39]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[46]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.964ns  (logic 0.288ns (29.876%)  route 0.676ns (70.124%))
  Logic Levels:           0  
  Clock Path Skew:        3.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.537ns
    Source Clock Delay      (SCD):    2.481ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.255ns (routing 0.777ns, distribution 1.478ns)
  Clock Net Delay (Destination): 2.464ns (routing 1.464ns, distribution 1.000ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.255     2.481    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X66Y183        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y183        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     2.769 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC/O
                         net (fo=1, routed)           0.676     3.445    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[46]
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[46]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.464     5.537    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[46]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.930ns  (logic 0.289ns (31.075%)  route 0.641ns (68.925%))
  Logic Levels:           0  
  Clock Path Skew:        3.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.535ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.462ns (routing 1.464ns, distribution 0.998ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X67Y184        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y184        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     2.789 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMA/O
                         net (fo=1, routed)           0.641     3.430    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[0]
    SLICE_X58Y192        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.462     5.535    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X58Y192        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[42]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.944ns  (logic 0.289ns (30.614%)  route 0.655ns (69.386%))
  Logic Levels:           0  
  Clock Path Skew:        3.105ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.586ns
    Source Clock Delay      (SCD):    2.481ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.255ns (routing 0.777ns, distribution 1.478ns)
  Clock Net Delay (Destination): 2.513ns (routing 1.464ns, distribution 1.049ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.255     2.481    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X66Y183        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y183        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     2.770 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMA/O
                         net (fo=1, routed)           0.655     3.425    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[42]
    SLICE_X64Y193        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[42]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.513     5.586    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y193        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[42]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[41]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.922ns  (logic 0.295ns (31.996%)  route 0.627ns (68.004%))
  Logic Levels:           0  
  Clock Path Skew:        3.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.537ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.464ns (routing 1.464ns, distribution 1.000ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X67Y183        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y183        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     2.795 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMG_D1/O
                         net (fo=1, routed)           0.627     3.422    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[41]
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[41]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.464     5.537    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[41]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.906ns  (logic 0.307ns (33.885%)  route 0.599ns (66.115%))
  Logic Levels:           0  
  Clock Path Skew:        3.083ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.584ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.274ns (routing 0.777ns, distribution 1.497ns)
  Clock Net Delay (Destination): 2.511ns (routing 1.464ns, distribution 1.047ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.274     2.500    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X67Y183        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y183        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     2.807 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/O
                         net (fo=1, routed)           0.599     3.406    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[33]
    SLICE_X64Y193        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.511     5.584    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y193        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[33]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[59]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.907ns  (logic 0.307ns (33.848%)  route 0.600ns (66.152%))
  Logic Levels:           0  
  Clock Path Skew:        3.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.537ns
    Source Clock Delay      (SCD):    2.499ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.273ns (routing 0.777ns, distribution 1.496ns)
  Clock Net Delay (Destination): 2.464ns (routing 1.464ns, distribution 1.000ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.273     2.499    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/WCLK
    SLICE_X67Y185        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y185        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     2.806 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB_D1/O
                         net (fo=1, routed)           0.600     3.406    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[59]
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[59]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.464     5.537    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X60Y194        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[59]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.040ns (32.000%)  route 0.085ns (68.000%))
  Logic Levels:           0  
  Clock Path Skew:        1.804ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.078ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.154ns (routing 0.421ns, distribution 0.733ns)
  Clock Net Delay (Destination): 1.671ns (routing 0.978ns, distribution 0.693ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.154     1.274    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y210        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.314 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.085     1.399    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.671     3.078    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.686%)  route 0.088ns (69.314%))
  Logic Levels:           0  
  Clock Path Skew:        1.811ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.083ns
    Source Clock Delay      (SCD):    1.272ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.152ns (routing 0.421ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.676ns (routing 0.978ns, distribution 0.698ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.152     1.272    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X57Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y216        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.311 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.088     1.399    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X55Y215        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.676     3.083    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X55Y215        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.039ns (28.467%)  route 0.098ns (71.533%))
  Logic Levels:           0  
  Clock Path Skew:        1.810ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.084ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.154ns (routing 0.421ns, distribution 0.733ns)
  Clock Net Delay (Destination): 1.677ns (routing 0.978ns, distribution 0.699ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.154     1.274    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y210        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.313 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.098     1.411    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X55Y211        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.677     3.084    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X55Y211        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.465%)  route 0.103ns (72.535%))
  Logic Levels:           0  
  Clock Path Skew:        1.804ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.078ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.154ns (routing 0.421ns, distribution 0.733ns)
  Clock Net Delay (Destination): 1.671ns (routing 0.978ns, distribution 0.693ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.154     1.274    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y210        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.313 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.103     1.416    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[0]
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.671     3.078    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        1.803ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.146ns
    Source Clock Delay      (SCD):    1.343ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.223ns (routing 0.421ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.739ns (routing 0.978ns, distribution 0.761ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.223     1.343    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X68Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y184        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.382 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.090     1.472    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X68Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.739     3.146    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X68Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        1.802ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.145ns
    Source Clock Delay      (SCD):    1.343ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.223ns (routing 0.421ns, distribution 0.802ns)
  Clock Net Delay (Destination): 1.738ns (routing 0.978ns, distribution 0.760ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.223     1.343    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X68Y185        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y185        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.382 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.090     1.472    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X68Y185        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.738     3.145    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X68Y185        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.198ns  (logic 0.039ns (19.697%)  route 0.159ns (80.303%))
  Logic Levels:           0  
  Clock Path Skew:        1.807ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.081ns
    Source Clock Delay      (SCD):    1.274ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.154ns (routing 0.421ns, distribution 0.733ns)
  Clock Net Delay (Destination): 1.674ns (routing 0.978ns, distribution 0.696ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.154     1.274    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y210        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.313 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.159     1.472    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.674     3.081    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.110ns (61.111%)  route 0.070ns (38.889%))
  Logic Levels:           0  
  Clock Path Skew:        1.777ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.085ns
    Source Clock Delay      (SCD):    1.308ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.188ns (routing 0.421ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.678ns (routing 0.978ns, distribution 0.700ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.188     1.308    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/WCLK
    SLICE_X48Y205        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y205        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.110     1.418 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMB/O
                         net (fo=1, routed)           0.070     1.488    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[58]
    SLICE_X49Y205        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.678     3.085    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X49Y205        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[58]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[63]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.185ns  (logic 0.111ns (60.000%)  route 0.074ns (40.000%))
  Logic Levels:           0  
  Clock Path Skew:        1.781ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.089ns
    Source Clock Delay      (SCD):    1.308ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.188ns (routing 0.421ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.682ns (routing 0.978ns, distribution 0.704ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.188     1.308    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/WCLK
    SLICE_X48Y205        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y205        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.111     1.419 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_63/RAMD_D1/O
                         net (fo=1, routed)           0.074     1.493    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[63]
    SLICE_X48Y204        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[63]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.682     3.089    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X48Y204        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[63]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.144ns  (logic 0.039ns (27.157%)  route 0.105ns (72.843%))
  Logic Levels:           0  
  Clock Path Skew:        1.804ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.158ns
    Source Clock Delay      (SCD):    1.354ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.234ns (routing 0.421ns, distribution 0.813ns)
  Clock Net Delay (Destination): 1.751ns (routing 0.978ns, distribution 0.773ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.234     1.354    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X74Y190        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y190        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.393 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.105     1.498    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X74Y190        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.751     3.158    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X74Y190        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay            97 Endpoints
Min Delay            97 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.468ns  (logic 0.000ns (0.000%)  route 2.468ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.293ns (routing 0.703ns, distribution 1.590ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[14]
                         net (fo=1, routed)           2.468     2.468    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/src_in
    SLICE_X109Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.293     2.475    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/dest_clk
    SLICE_X109Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.303ns  (logic 0.000ns (0.000%)  route 2.303ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.296ns (routing 0.703ns, distribution 1.593ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.303     2.303    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/src_in
    SLICE_X109Y112       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.296     2.478    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/dest_clk
    SLICE_X109Y112       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac13_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.283ns  (logic 0.000ns (0.000%)  route 2.283ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.288ns (routing 0.703ns, distribution 1.585ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[14]
                         net (fo=1, routed)           2.283     2.283    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/src_in
    SLICE_X108Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.288     2.470    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/dest_clk
    SLICE_X108Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.279ns  (logic 0.000ns (0.000%)  route 2.279ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.290ns (routing 0.703ns, distribution 1.587ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC2[15]
                         net (fo=1, routed)           2.279     2.279    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/src_in
    SLICE_X108Y112       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.290     2.472    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/dest_clk
    SLICE_X108Y112       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac12_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.231ns  (logic 0.000ns (0.000%)  route 2.231ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.257ns (routing 0.703ns, distribution 1.554ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                         net (fo=2, routed)           2.231     2.231    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/src_in
    SLICE_X107Y120       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.257     2.439    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/dest_clk
    SLICE_X107Y120       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_powerup_state_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.150ns  (logic 0.000ns (0.000%)  route 2.150ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[15]
                         net (fo=1, routed)           2.150     2.150    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/src_in
    SLICE_X109Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/dest_clk
    SLICE_X109Y108       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.139ns  (logic 0.000ns (0.000%)  route 2.139ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           2.139     2.139    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/src_in
    SLICE_X108Y119       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/dest_clk
    SLICE_X108Y119       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_supplies_up_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.133ns  (logic 0.000ns (0.000%)  route 2.133ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.287ns (routing 0.703ns, distribution 1.584ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC1[14]
                         net (fo=1, routed)           2.133     2.133    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/src_in
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.287     2.469    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/dest_clk
    SLICE_X108Y107       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac11_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.103ns  (logic 0.000ns (0.000%)  route 2.103ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.286ns (routing 0.703ns, distribution 1.583ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_DAC0[15]
                         net (fo=1, routed)           2.103     2.103    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/src_in
    SLICE_X108Y105       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.286     2.468    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/dest_clk
    SLICE_X108Y105       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac10_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.086ns  (logic 0.000ns (0.000%)  route 2.086ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.307ns (routing 0.703ns, distribution 1.604ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                         net (fo=2, routed)           2.086     2.086    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/src_in
    SLICE_X110Y119       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.307     2.489    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/dest_clk
    SLICE_X110Y119       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_pll_lock_i/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.138ns  (logic 0.000ns (0.000%)  route 0.138ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.590ns (routing 0.472ns, distribution 1.118ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[15]
                         net (fo=1, routed)           0.138     0.138    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/src_in
    SLICE_X118Y82        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.590     1.737    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/dest_clk
    SLICE_X118Y82        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.200ns  (logic 0.000ns (0.000%)  route 0.200ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.590ns (routing 0.472ns, distribution 1.118ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[14]
                         net (fo=1, routed)           0.200     0.200    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/src_in
    SLICE_X116Y80        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.590     1.737    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/dest_clk
    SLICE_X116Y80        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.204ns  (logic 0.000ns (0.000%)  route 0.204ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.600ns (routing 0.472ns, distribution 1.128ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[3]
                         net (fo=1, routed)           0.204     0.204    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/src_in
    SLICE_X115Y77        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.600     1.747    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/dest_clk
    SLICE_X115Y77        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.218ns  (logic 0.000ns (0.000%)  route 0.218ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.597ns (routing 0.472ns, distribution 1.125ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC0[15]
                         net (fo=1, routed)           0.218     0.218    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/src_in
    SLICE_X115Y81        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.597     1.744    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/dest_clk
    SLICE_X115Y81        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc10_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.237ns  (logic 0.000ns (0.000%)  route 0.237ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.582ns (routing 0.472ns, distribution 1.110ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[14]
                         net (fo=1, routed)           0.237     0.237    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/src_in
    SLICE_X117Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.582     1.729    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/dest_clk
    SLICE_X117Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.237ns  (logic 0.000ns (0.000%)  route 0.237ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.581ns (routing 0.472ns, distribution 1.109ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC2[15]
                         net (fo=1, routed)           0.237     0.237    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/src_in
    SLICE_X118Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.581     1.728    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/dest_clk
    SLICE_X118Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc12_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.240ns  (logic 0.000ns (0.000%)  route 0.240ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC1[2]
                         net (fo=1, routed)           0.240     0.240    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/src_in
    SLICE_X109Y76        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/dest_clk
    SLICE_X109Y76        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc11_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.242ns  (logic 0.000ns (0.000%)  route 0.242ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.588ns (routing 0.472ns, distribution 1.116ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.242     0.242    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_over_range/src_in
    SLICE_X117Y80        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.588     1.735    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_over_range/dest_clk
    SLICE_X117Y80        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc03_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.245ns  (logic 0.000ns (0.000%)  route 0.245ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.582ns (routing 0.472ns, distribution 1.110ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.245     0.245    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/src_in
    SLICE_X117Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.582     1.729    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/dest_clk
    SLICE_X117Y93        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.252ns  (logic 0.000ns (0.000%)  route 0.252ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.582ns (routing 0.472ns, distribution 1.110ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_ADC3[14]
                         net (fo=1, routed)           0.252     0.252    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_data_irq/src_in
    SLICE_X118Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.582     1.729    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_data_irq/dest_clk
    SLICE_X118Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc13_data_irq/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.329ns  (logic 1.063ns (31.932%)  route 2.266ns (68.068%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.877     1.413    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[10]
    SLICE_X115Y90        LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.100     1.513 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.409     1.922    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_0
    SLICE_X115Y91        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     2.072 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20/O
                         net (fo=1, routed)           0.206     2.278    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20_n_0
    SLICE_X115Y98        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     2.331 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12/O
                         net (fo=1, routed)           0.476     2.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_n_0
    SLICE_X110Y95        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     2.932 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.226     3.158    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.099     3.257 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.072     3.329    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.241ns  (logic 1.303ns (40.204%)  route 1.938ns (59.796%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.703ns, distribution 1.546ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.886     1.674    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[8]
    SLICE_X115Y91        LUT3 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.135     1.809 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.264     2.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_0
    SLICE_X115Y91        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     2.172 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.203     2.375    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X115Y98        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.088     2.463 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.092     2.555    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X114Y98        LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     2.652 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.443     3.095    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.191 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     3.241    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.886ns  (logic 1.113ns (38.565%)  route 1.773ns (61.435%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.779     1.477    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[11]
    SLICE_X114Y89        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.097     1.574 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_28/O
                         net (fo=1, routed)           0.429     2.003    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_28_n_0
    SLICE_X109Y90        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.100     2.103 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                         net (fo=1, routed)           0.292     2.395    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    SLICE_X114Y90        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.096     2.491 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4/O
                         net (fo=1, routed)           0.201     2.692    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.122     2.814 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.886    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.754ns  (logic 1.184ns (42.992%)  route 1.570ns (57.008%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.418ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.236ns (routing 0.703ns, distribution 1.533ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.871     1.642    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[10]
    SLICE_X115Y93        LUT4 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.090     1.732 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_35/O
                         net (fo=1, routed)           0.094     1.826    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_35_n_0
    SLICE_X115Y93        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     1.925 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18/O
                         net (fo=1, routed)           0.049     1.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18_n_0
    SLICE_X115Y93        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.125     2.099 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.507     2.606    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     2.705 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     2.754    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.236     2.418    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.752ns  (logic 0.979ns (35.574%)  route 1.773ns (64.426%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.914     1.502    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[11]
    SLICE_X115Y91        LUT3 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.090     1.592 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.041     1.633    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_0
    SLICE_X115Y91        LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.088     1.721 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.203     1.924    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X115Y98        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.052     1.976 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.205     2.181    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     2.305 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.344     2.649    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     2.686 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.066     2.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.464ns  (logic 0.884ns (35.877%)  route 1.580ns (64.123%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.983     1.594    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[9]
    SLICE_X116Y91        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     1.740 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.194     1.934    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X115Y96        LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     2.024 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.331     2.355    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     2.392 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.072     2.464    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.286ns  (logic 0.798ns (34.908%)  route 1.488ns (65.092%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.832     1.357    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[12]
    SLICE_X114Y89        LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.089     1.446 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36/O
                         net (fo=1, routed)           0.113     1.559    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36_n_0
    SLICE_X114Y90        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.036     1.595 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                         net (fo=1, routed)           0.041     1.636    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    SLICE_X114Y90        LUT6 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.050     1.686 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.436     2.122    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.098     2.220 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     2.286    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.172ns  (logic 0.866ns (39.871%)  route 1.306ns (60.129%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.475ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.475ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.293ns (routing 0.703ns, distribution 1.590ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.847     1.379    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[8]
    SLICE_X116Y91        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.123     1.502 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11/O
                         net (fo=1, routed)           0.239     1.741    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11_n_0
    SLICE_X114Y99        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.123     1.864 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.148     2.012    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.088     2.100 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.072     2.172    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.293     2.475    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.010ns  (logic 0.363ns (35.941%)  route 0.647ns (64.059%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.732ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.732ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.422     0.650    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[8]
    SLICE_X116Y91        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     0.700 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11/O
                         net (fo=1, routed)           0.123     0.823    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11_n_0
    SLICE_X114Y99        LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     0.873 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.076     0.949    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.035     0.984 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.026     1.010    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.078ns  (logic 0.362ns (33.581%)  route 0.716ns (66.419%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.412     0.662    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[12]
    SLICE_X114Y89        LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.035     0.697 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36/O
                         net (fo=1, routed)           0.056     0.753    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_36_n_0
    SLICE_X114Y90        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.015     0.768 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15/O
                         net (fo=1, routed)           0.023     0.791    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_n_0
    SLICE_X114Y90        LUT6 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.022     0.813 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.201     1.014    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.040     1.054 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.078    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.137ns  (logic 0.382ns (33.597%)  route 0.755ns (66.403%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.737ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.737ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.590ns (routing 0.472ns, distribution 1.118ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.459     0.733    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[9]
    SLICE_X116Y91        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     0.792 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.102     0.894    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X115Y96        LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.035     0.929 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.168     1.097    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     1.111 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.026     1.137    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.590     1.737    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.206ns  (logic 0.408ns (33.831%)  route 0.798ns (66.169%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.693ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.693ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.546ns (routing 0.472ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.433     0.674    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[10]
    SLICE_X115Y93        LUT4 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.035     0.709 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_35/O
                         net (fo=1, routed)           0.049     0.758    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_35_n_0
    SLICE_X115Y93        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.041     0.799 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18/O
                         net (fo=1, routed)           0.027     0.826    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_18_n_0
    SLICE_X115Y93        LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.050     0.876 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.273     1.149    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.190 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.206    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.546     1.693    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.279ns  (logic 0.456ns (35.653%)  route 0.823ns (64.347%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.381     0.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[11]
    SLICE_X114Y89        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.040     0.706 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_28/O
                         net (fo=1, routed)           0.185     0.891    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_28_n_0
    SLICE_X109Y90        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.041     0.932 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                         net (fo=1, routed)           0.127     1.059    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    SLICE_X114Y90        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.040     1.099 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4/O
                         net (fo=1, routed)           0.104     1.203    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_4_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.050     1.253 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.279    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.302ns  (logic 0.421ns (32.335%)  route 0.881ns (67.665%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.450     0.715    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[11]
    SLICE_X115Y91        LUT3 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.035     0.750 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[11]_i_29/O
                         net (fo=1, routed)           0.024     0.774    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_0
    SLICE_X115Y91        LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.035     0.809 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18/O
                         net (fo=1, routed)           0.106     0.915    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_18_n_0
    SLICE_X115Y98        LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.022     0.937 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.100     1.037    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.050     1.087 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.177     1.264    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     1.278 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.024     1.302    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.426ns  (logic 0.441ns (30.926%)  route 0.985ns (69.074%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        1.701ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.472ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.443     0.680    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[8]
    SLICE_X115Y91        LUT3 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.048     0.728 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.133     0.861    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_0
    SLICE_X115Y91        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.041     0.902 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.108     1.010    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X115Y98        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.035     1.045 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.049     1.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X114Y98        LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.040     1.134 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.235     1.369    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.409 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.426    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC0_CLK  {rise@0.000ns fall@1.953ns period=3.906ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.554ns  (logic 0.443ns (28.507%)  route 1.111ns (71.493%))
  Logic Levels:           5  (LUT3=1 LUT6=4)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.435     0.662    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc0_common_stat[10]
    SLICE_X115Y90        LUT3 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.041     0.703 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.185     0.888    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_0
    SLICE_X115Y91        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.060     0.948 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20/O
                         net (fo=1, routed)           0.109     1.057    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20_n_0
    SLICE_X115Y98        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     1.080 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12/O
                         net (fo=1, routed)           0.240     1.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_n_0
    SLICE_X110Y95        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.051     1.371 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.116     1.487    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.041     1.528 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.026     1.554    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.995ns  (logic 1.282ns (42.805%)  route 1.713ns (57.195%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.703ns, distribution 1.546ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.509     1.297    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[8]
    SLICE_X112Y90        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     1.334 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_33/O
                         net (fo=1, routed)           0.105     1.439    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_33_n_0
    SLICE_X110Y90        LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.124     1.563 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_23/O
                         net (fo=1, routed)           0.223     1.786    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_23_n_0
    SLICE_X112Y95        LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.148     1.934 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.383     2.317    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X114Y98        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.089     2.406 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.443     2.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     2.945 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     2.995    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.787ns  (logic 1.194ns (42.842%)  route 1.593ns (57.158%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.418ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.236ns (routing 0.703ns, distribution 1.533ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.583     1.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[13]
    SLICE_X113Y88        LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.123     1.477 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_39/O
                         net (fo=1, routed)           0.100     1.577    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_39_n_0
    SLICE_X112Y88        LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.052     1.629 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19/O
                         net (fo=1, routed)           0.354     1.983    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19_n_0
    SLICE_X115Y93        LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.149     2.132 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.507     2.639    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     2.738 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     2.787    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.236     2.418    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.424ns  (logic 1.244ns (51.320%)  route 1.180ns (48.680%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.558     1.256    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[14]
    SLICE_X113Y90        LUT4 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.148     1.404 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_49/O
                         net (fo=1, routed)           0.059     1.463    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_49_n_0
    SLICE_X113Y90        LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     1.611 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_36/O
                         net (fo=1, routed)           0.153     1.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_36_n_0
    SLICE_X111Y90        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     1.815 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.235     2.050    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X112Y94        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.148     2.198 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.103     2.301    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.051     2.352 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.251ns  (logic 0.974ns (43.270%)  route 1.277ns (56.730%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.460     1.048    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[11]
    SLICE_X111Y91        LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     1.099 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_37/O
                         net (fo=1, routed)           0.057     1.156    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_37_n_0
    SLICE_X111Y91        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.148     1.304 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26/O
                         net (fo=1, routed)           0.140     1.444    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26_n_0
    SLICE_X111Y95        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.099     1.543 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_10/O
                         net (fo=1, routed)           0.210     1.753    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_10_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.051     1.804 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.344     2.148    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     2.185 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.066     2.251    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.205ns  (logic 1.004ns (45.533%)  route 1.201ns (54.467%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.581     1.192    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[12]
    SLICE_X111Y89        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.089     1.281 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_34/O
                         net (fo=1, routed)           0.039     1.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_34_n_0
    SLICE_X111Y89        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     1.356 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12/O
                         net (fo=1, routed)           0.359     1.715    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12_n_0
    SLICE_X110Y96        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.123     1.838 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.150     1.988    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.145     2.133 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.072     2.205    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.076ns  (logic 0.927ns (44.653%)  route 1.149ns (55.347%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.475ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.475ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.293ns (routing 0.703ns, distribution 1.590ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.434     0.966    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[9]
    SLICE_X113Y92        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.100     1.066 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_32/O
                         net (fo=1, routed)           0.296     1.362    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_32_n_0
    SLICE_X110Y92        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.051     1.413 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.177     1.590    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X112Y93        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     1.689 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.170     1.859    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145     2.004 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.072     2.076    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.293     2.475    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.883ns  (logic 0.869ns (46.150%)  route 1.014ns (53.850%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.429     0.965    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[10]
    SLICE_X111Y90        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     1.000 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_36/O
                         net (fo=1, routed)           0.088     1.088    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_36_n_0
    SLICE_X110Y90        LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     1.125 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27/O
                         net (fo=1, routed)           0.157     1.282    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27_n_0
    SLICE_X110Y95        LUT5 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.123     1.405 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.042     1.447    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X110Y95        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     1.486 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.226     1.712    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.099     1.811 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.072     1.883    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.843ns  (logic 0.808ns (43.842%)  route 1.035ns (56.158%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.641     1.166    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[15]
    SLICE_X112Y91        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.052     1.218 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_48/O
                         net (fo=1, routed)           0.089     1.307    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_48_n_0
    SLICE_X112Y91        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     1.397 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21/O
                         net (fo=1, routed)           0.097     1.494    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21_n_0
    SLICE_X112Y93        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     1.584 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.142     1.726    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.051     1.777 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     1.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.848ns  (logic 0.364ns (42.925%)  route 0.484ns (57.075%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.285     0.535    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[15]
    SLICE_X112Y91        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.022     0.557 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_48/O
                         net (fo=1, routed)           0.047     0.604    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_48_n_0
    SLICE_X112Y91        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.035     0.639 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21/O
                         net (fo=1, routed)           0.052     0.691    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_21_n_0
    SLICE_X112Y93        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.035     0.726 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.076     0.802    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.022     0.824 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     0.848    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.858ns  (logic 0.361ns (42.075%)  route 0.497ns (57.925%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.203     0.430    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[10]
    SLICE_X111Y90        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.014     0.444 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_36/O
                         net (fo=1, routed)           0.044     0.488    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_36_n_0
    SLICE_X110Y90        LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.014     0.502 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27/O
                         net (fo=1, routed)           0.083     0.585    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_27_n_0
    SLICE_X110Y95        LUT5 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.050     0.635 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16/O
                         net (fo=1, routed)           0.025     0.660    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_16_n_0
    SLICE_X110Y95        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     0.675 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.116     0.791    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.041     0.832 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.026     0.858    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.919ns  (logic 0.390ns (42.437%)  route 0.529ns (57.563%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.732ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.732ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.200     0.428    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[9]
    SLICE_X113Y92        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.040     0.468 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_32/O
                         net (fo=1, routed)           0.126     0.594    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_32_n_0
    SLICE_X110Y92        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.022     0.616 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17/O
                         net (fo=1, routed)           0.087     0.703    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_17_n_0
    SLICE_X112Y93        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.041     0.744 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.090     0.834    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.059     0.893 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.026     0.919    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.013ns  (logic 0.433ns (42.744%)  route 0.580ns (57.256%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.737ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.737ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.590ns (routing 0.472ns, distribution 1.118ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.277     0.551    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[12]
    SLICE_X111Y89        LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     0.586 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_34/O
                         net (fo=1, routed)           0.021     0.607    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_34_n_0
    SLICE_X111Y89        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     0.622 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12/O
                         net (fo=1, routed)           0.181     0.803    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12_n_0
    SLICE_X110Y96        LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.050     0.853 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.075     0.928    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.059     0.987 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.026     1.013    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.590     1.737    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.056ns  (logic 0.424ns (40.152%)  route 0.632ns (59.848%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.218     0.483    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[11]
    SLICE_X111Y91        LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.022     0.505 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_37/O
                         net (fo=1, routed)           0.031     0.536    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_37_n_0
    SLICE_X111Y91        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.059     0.595 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26/O
                         net (fo=1, routed)           0.076     0.671    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26_n_0
    SLICE_X111Y95        LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.041     0.712 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_10/O
                         net (fo=1, routed)           0.106     0.818    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_10_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.023     0.841 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.177     1.018    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     1.032 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.024     1.056    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.087ns  (logic 0.507ns (46.642%)  route 0.580ns (53.358%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.267     0.552    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[14]
    SLICE_X113Y90        LUT4 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.059     0.611 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_49/O
                         net (fo=1, routed)           0.033     0.644    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_49_n_0
    SLICE_X113Y90        LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.059     0.703 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_36/O
                         net (fo=1, routed)           0.080     0.783    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_36_n_0
    SLICE_X111Y90        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.023     0.806 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17/O
                         net (fo=1, routed)           0.117     0.923    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_17_n_0
    SLICE_X112Y94        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.059     0.982 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.057     1.039    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.022     1.061 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.087    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.201ns  (logic 0.414ns (34.471%)  route 0.787ns (65.529%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.693ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.693ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.546ns (routing 0.472ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.271     0.512    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[13]
    SLICE_X113Y88        LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.050     0.562 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_39/O
                         net (fo=1, routed)           0.052     0.614    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_39_n_0
    SLICE_X112Y88        LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.022     0.636 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19/O
                         net (fo=1, routed)           0.175     0.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_19_n_0
    SLICE_X115Y93        LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.060     0.871 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.273     1.144    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.185 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.201    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.546     1.693    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.291ns  (logic 0.434ns (33.617%)  route 0.857ns (66.383%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Path Skew:        1.701ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.472ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.243     0.480    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[8]
    SLICE_X112Y90        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     0.494 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_33/O
                         net (fo=1, routed)           0.055     0.549    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_33_n_0
    SLICE_X110Y90        LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.049     0.598 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_23/O
                         net (fo=1, routed)           0.118     0.716    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_23_n_0
    SLICE_X112Y95        LUT5 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.059     0.775 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10/O
                         net (fo=1, routed)           0.189     0.964    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_10_n_0
    SLICE_X114Y98        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.035     0.999 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.235     1.234    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.274 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.291    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.137ns  (logic 1.222ns (38.954%)  route 1.915ns (61.046%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.418ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.236ns (routing 0.703ns, distribution 1.533ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.906     1.677    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[13]
    SLICE_X112Y93        LUT4 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.052     1.729 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_57/O
                         net (fo=1, routed)           0.099     1.828    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_57_n_0
    SLICE_X112Y93        LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.123     1.951 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_42/O
                         net (fo=1, routed)           0.315     2.266    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_42_n_0
    SLICE_X115Y93        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.088     2.354 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20/O
                         net (fo=1, routed)           0.039     2.393    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20_n_0
    SLICE_X115Y93        LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.089     2.482 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.507     2.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     3.088 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     3.137    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.236     2.418    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.911ns  (logic 1.183ns (40.639%)  route 1.728ns (59.361%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.703ns, distribution 1.546ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.837     1.625    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[8]
    SLICE_X115Y91        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     1.676 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30/O
                         net (fo=1, routed)           0.104     1.780    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30_n_0
    SLICE_X114Y91        LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     1.928 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                         net (fo=1, routed)           0.084     2.012    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    SLICE_X114Y92        LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.051     2.063 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/O
                         net (fo=1, routed)           0.210     2.273    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9_n_0
    SLICE_X114Y98        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.049     2.322 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.443     2.765    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     2.861 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     2.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.693ns  (logic 1.123ns (41.701%)  route 1.570ns (58.299%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.888     1.586    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[14]
    SLICE_X117Y90        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.089     1.675 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_54/O
                         net (fo=1, routed)           0.131     1.806    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_54_n_0
    SLICE_X117Y89        LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.099     1.905 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.130     2.035    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X116Y89        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.051     2.086 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_18/O
                         net (fo=1, routed)           0.211     2.297    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_18_n_0
    SLICE_X114Y94        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.149     2.446 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.138     2.584    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.037     2.621 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     2.693    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.592ns  (logic 0.914ns (35.262%)  route 1.678ns (64.738%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.901     1.437    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[10]
    SLICE_X116Y94        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     1.473 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33/O
                         net (fo=1, routed)           0.287     1.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33_n_0
    SLICE_X110Y94        LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.100     1.860 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25/O
                         net (fo=1, routed)           0.048     1.908    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25_n_0
    SLICE_X110Y94        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.053     1.961 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15/O
                         net (fo=1, routed)           0.144     2.105    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15_n_0
    SLICE_X110Y95        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.195 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.226     2.421    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.099     2.520 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.072     2.592    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.570ns  (logic 1.026ns (39.922%)  route 1.544ns (60.078%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.854     1.442    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[11]
    SLICE_X115Y92        LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     1.532 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33/O
                         net (fo=1, routed)           0.053     1.585    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33_n_0
    SLICE_X115Y92        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     1.708 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_24/O
                         net (fo=1, routed)           0.087     1.795    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_24_n_0
    SLICE_X114Y92        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.089     1.884 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.140     2.024    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099     2.123 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.344     2.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     2.504 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.066     2.570    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.554ns  (logic 0.880ns (34.456%)  route 1.674ns (65.544%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.900     1.425    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[15]
    SLICE_X116Y90        LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.099     1.524 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_86/O
                         net (fo=1, routed)           0.197     1.721    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_86_n_0
    SLICE_X116Y89        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.149     1.870 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_54/O
                         net (fo=1, routed)           0.040     1.910    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_54_n_0
    SLICE_X116Y89        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.035     1.945 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24/O
                         net (fo=1, routed)           0.289     2.234    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24_n_0
    SLICE_X114Y94        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     2.269 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                         net (fo=1, routed)           0.182     2.451    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.037     2.488 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     2.554    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.457ns  (logic 1.011ns (41.148%)  route 1.446ns (58.852%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        2.475ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.475ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.293ns (routing 0.703ns, distribution 1.590ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.783     1.315    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[9]
    SLICE_X116Y94        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     1.350 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_40/O
                         net (fo=1, routed)           0.276     1.626    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_40_n_0
    SLICE_X110Y93        LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.123     1.749 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_34/O
                         net (fo=1, routed)           0.050     1.799    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_34_n_0
    SLICE_X110Y93        LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.125     1.924 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18/O
                         net (fo=1, routed)           0.095     2.019    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18_n_0
    SLICE_X112Y93        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     2.070 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.170     2.240    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145     2.385 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.072     2.457    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.293     2.475    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.115ns  (logic 0.945ns (44.681%)  route 1.170ns (55.319%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.906     1.517    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[12]
    SLICE_X110Y96        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.152     1.669 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.042     1.711    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X110Y96        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.037     1.748 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.150     1.898    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.145     2.043 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.072     2.115    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.982ns  (logic 0.408ns (41.548%)  route 0.574ns (58.452%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.737ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.737ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.590ns (routing 0.472ns, distribution 1.118ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.449     0.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[12]
    SLICE_X110Y96        LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.061     0.784 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14/O
                         net (fo=1, routed)           0.024     0.808    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_14_n_0
    SLICE_X110Y96        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.014     0.822 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.075     0.897    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.059     0.956 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.026     0.982    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.590     1.737    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.140ns  (logic 0.423ns (37.105%)  route 0.717ns (62.895%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.732ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.732ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.382     0.610    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[9]
    SLICE_X116Y94        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.014     0.624 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_40/O
                         net (fo=1, routed)           0.141     0.765    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_40_n_0
    SLICE_X110Y93        LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.050     0.815 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_34/O
                         net (fo=1, routed)           0.028     0.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_34_n_0
    SLICE_X110Y93        LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.050     0.893 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18/O
                         net (fo=1, routed)           0.050     0.943    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_18_n_0
    SLICE_X112Y93        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.022     0.965 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.090     1.055    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.059     1.114 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.026     1.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.210ns  (logic 0.381ns (31.488%)  route 0.829ns (68.512%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.449     0.676    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[10]
    SLICE_X116Y94        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     0.691 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33/O
                         net (fo=1, routed)           0.142     0.833    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33_n_0
    SLICE_X110Y94        LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.040     0.873 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25/O
                         net (fo=1, routed)           0.027     0.900    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_25_n_0
    SLICE_X110Y94        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.023     0.923 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15/O
                         net (fo=1, routed)           0.069     0.992    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_15_n_0
    SLICE_X110Y95        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     1.027 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.116     1.143    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.041     1.184 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.026     1.210    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.211ns  (logic 0.440ns (36.334%)  route 0.771ns (63.666%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.421     0.686    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[11]
    SLICE_X115Y92        LUT4 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.035     0.721 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33/O
                         net (fo=1, routed)           0.029     0.750    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_33_n_0
    SLICE_X115Y92        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.050     0.800 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_24/O
                         net (fo=1, routed)           0.047     0.847    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_24_n_0
    SLICE_X114Y92        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     0.882 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9/O
                         net (fo=1, routed)           0.073     0.955    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_9_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.041     0.996 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.177     1.173    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     1.187 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.024     1.211    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.214ns  (logic 0.393ns (32.372%)  route 0.821ns (67.628%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.447     0.697    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[15]
    SLICE_X116Y90        LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.041     0.738 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_86/O
                         net (fo=1, routed)           0.099     0.837    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_86_n_0
    SLICE_X116Y89        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.060     0.897 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_54/O
                         net (fo=1, routed)           0.024     0.921    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_54_n_0
    SLICE_X116Y89        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.014     0.935 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24/O
                         net (fo=1, routed)           0.142     1.077    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24_n_0
    SLICE_X114Y94        LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.014     1.091 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                         net (fo=1, routed)           0.085     1.176    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     1.190 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.214    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.235ns  (logic 0.458ns (37.085%)  route 0.777ns (62.915%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.440     0.725    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[14]
    SLICE_X117Y90        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     0.760 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_54/O
                         net (fo=1, routed)           0.069     0.829    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_54_n_0
    SLICE_X117Y89        LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.041     0.870 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38/O
                         net (fo=1, routed)           0.069     0.939    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_38_n_0
    SLICE_X116Y89        LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.023     0.962 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_18/O
                         net (fo=1, routed)           0.105     1.067    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_18_n_0
    SLICE_X114Y94        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.060     1.127 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.068     1.195    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.014     1.209 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.235    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.276ns  (logic 0.402ns (31.505%)  route 0.874ns (68.495%))
  Logic Levels:           5  (LUT4=2 LUT6=3)
  Clock Path Skew:        1.701ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.472ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.414     0.651    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[8]
    SLICE_X115Y91        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.022     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30/O
                         net (fo=1, routed)           0.056     0.729    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_30_n_0
    SLICE_X114Y91        LUT4 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.059     0.788 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21/O
                         net (fo=1, routed)           0.045     0.833    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_21_n_0
    SLICE_X114Y92        LUT6 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.022     0.855 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9/O
                         net (fo=1, routed)           0.107     0.962    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_9_n_0
    SLICE_X114Y98        LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.022     0.984 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.235     1.219    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.259 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.276    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC2_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.370ns  (logic 0.424ns (30.949%)  route 0.946ns (69.051%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.693ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.693ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.546ns (routing 0.472ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y2           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y2           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.449     0.690    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc2_common_stat[13]
    SLICE_X112Y93        LUT4 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.022     0.712 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_57/O
                         net (fo=1, routed)           0.049     0.761    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_57_n_0
    SLICE_X112Y93        LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.050     0.811 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_42/O
                         net (fo=1, routed)           0.137     0.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_42_n_0
    SLICE_X115Y93        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.035     0.983 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20/O
                         net (fo=1, routed)           0.022     1.005    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20_n_0
    SLICE_X115Y93        LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.035     1.040 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.273     1.313    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.354 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.370    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.546     1.693    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.465ns  (logic 1.210ns (34.921%)  route 2.255ns (65.079%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.418ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.236ns (routing 0.703ns, distribution 1.533ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.771     0.771 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.283     2.054    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[13]
    SLICE_X116Y98        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.088     2.142 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_59/O
                         net (fo=1, routed)           0.064     2.206    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_59_n_0
    SLICE_X116Y98        LUT5 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     2.355 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_43/O
                         net (fo=1, routed)           0.044     2.399    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_43_n_0
    SLICE_X116Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     2.450 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.308     2.758    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X115Y93        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.052     2.810 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.507     3.317    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.099     3.416 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     3.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.236     2.418    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.293ns  (logic 1.142ns (34.680%)  route 2.151ns (65.320%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.703ns, distribution 1.546ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.788     0.788 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.230     2.018    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[8]
    SLICE_X117Y99        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.149     2.167 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28/O
                         net (fo=1, routed)           0.183     2.350    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28_n_0
    SLICE_X115Y99        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     2.389 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.095     2.484    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X114Y100       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     2.519 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.150     2.669    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X114Y98        LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.035     2.704 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.443     3.147    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.243 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     3.293    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.093ns  (logic 0.959ns (31.005%)  route 2.134ns (68.994%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.698     0.698 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.600     2.298    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[14]
    SLICE_X112Y97        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.051     2.349 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_32/O
                         net (fo=1, routed)           0.176     2.525    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_32_n_0
    SLICE_X112Y97        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.122     2.647 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_16/O
                         net (fo=1, routed)           0.183     2.830    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_16_n_0
    SLICE_X112Y94        LUT5 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.037     2.867 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.103     2.970    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.051     3.021 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     3.093    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.014ns  (logic 0.896ns (29.728%)  route 2.118ns (70.272%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.588     0.588 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.196     1.784    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[11]
    SLICE_X117Y99        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     1.820 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_32/O
                         net (fo=1, routed)           0.194     2.014    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_32_n_0
    SLICE_X114Y99        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.049     2.063 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.090     2.153    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X114Y100       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.036     2.189 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/O
                         net (fo=1, routed)           0.228     2.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.150     2.567 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.344     2.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     2.948 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.066     3.014    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.983ns  (logic 1.025ns (34.361%)  route 1.958ns (65.639%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.536     0.536 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.311     1.847    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[10]
    SLICE_X112Y99        LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.148     1.995 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32/O
                         net (fo=1, routed)           0.040     2.035    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32_n_0
    SLICE_X112Y99        LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.037     2.072 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.048     2.120    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X112Y99        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.053     2.173 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.261     2.434    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X110Y95        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.152     2.586 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.226     2.812    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.099     2.911 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.072     2.983    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.980ns  (logic 0.885ns (29.698%)  route 2.095ns (70.302%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.611     0.611 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.541     2.152    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[12]
    SLICE_X116Y97        LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.035     2.187 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_41/O
                         net (fo=1, routed)           0.153     2.340    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_41_n_0
    SLICE_X114Y97        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.090     2.430 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.041     2.471    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X114Y97        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     2.521 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.288     2.809    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.099     2.908 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.072     2.980    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.716ns  (logic 0.740ns (27.246%)  route 1.976ns (72.754%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.525     0.525 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.516     2.041    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[15]
    SLICE_X112Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.131 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_43/O
                         net (fo=1, routed)           0.160     2.291    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_43_n_0
    SLICE_X112Y96        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.037     2.328 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20/O
                         net (fo=1, routed)           0.092     2.420    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20_n_0
    SLICE_X112Y93        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.037     2.457 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.142     2.599    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.051     2.650 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     2.716    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.530ns  (logic 0.863ns (34.111%)  route 1.667ns (65.889%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.475ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.475ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.293ns (routing 0.703ns, distribution 1.590ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.532     0.532 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.403     1.935    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[9]
    SLICE_X113Y99        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.051     1.986 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_30/O
                         net (fo=1, routed)           0.043     2.029    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_30_n_0
    SLICE_X113Y99        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.119 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.044     2.163    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X113Y99        LUT4 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.091     2.254 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.105     2.359    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.099     2.458 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.072     2.530    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.293     2.475    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.193ns  (logic 0.361ns (30.260%)  route 0.832ns (69.740%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.732ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.732ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[9])
                                                      0.228     0.228 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.701     0.929    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[9]
    SLICE_X113Y99        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.022     0.951 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_30/O
                         net (fo=1, routed)           0.023     0.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_30_n_0
    SLICE_X113Y99        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     1.009 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.025     1.034    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X113Y99        LUT4 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.035     1.069 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.057     1.126    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.041     1.167 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.026     1.193    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.299ns  (logic 0.335ns (25.789%)  route 0.964ns (74.211%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[15])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.736     0.986    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[15]
    SLICE_X112Y98        LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     1.021 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_43/O
                         net (fo=1, routed)           0.080     1.101    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_43_n_0
    SLICE_X112Y96        LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.014     1.115 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20/O
                         net (fo=1, routed)           0.048     1.163    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20_n_0
    SLICE_X112Y93        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.014     1.177 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.076     1.253    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.022     1.275 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.299    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.404ns  (logic 0.425ns (30.271%)  route 0.979ns (69.729%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[10])
                                                      0.227     0.227 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.657     0.884    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[10]
    SLICE_X112Y99        LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.059     0.943 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32/O
                         net (fo=1, routed)           0.023     0.966    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_32_n_0
    SLICE_X112Y99        LUT5 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.014     0.980 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23/O
                         net (fo=1, routed)           0.027     1.007    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_23_n_0
    SLICE_X112Y99        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.023     1.030 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.130     1.160    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X110Y95        LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.061     1.221 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.116     1.337    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.041     1.378 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.026     1.404    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.411ns  (logic 0.387ns (27.427%)  route 1.024ns (72.573%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.737ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.737ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.590ns (routing 0.472ns, distribution 1.118ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[12])
                                                      0.274     0.274 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.778     1.052    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[12]
    SLICE_X116Y97        LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.014     1.066 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_41/O
                         net (fo=1, routed)           0.074     1.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_41_n_0
    SLICE_X114Y97        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.036     1.176 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.023     1.199    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X114Y97        LUT5 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.022     1.221 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.123     1.344    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.041     1.385 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.026     1.411    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.590     1.737    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.448ns  (logic 0.390ns (26.934%)  route 1.058ns (73.066%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[11])
                                                      0.265     0.265 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.598     0.863    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[11]
    SLICE_X117Y99        LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     0.878 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_32/O
                         net (fo=1, routed)           0.100     0.978    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_32_n_0
    SLICE_X114Y99        LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.022     1.000 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22/O
                         net (fo=1, routed)           0.045     1.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_22_n_0
    SLICE_X114Y100       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.014     1.059 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/O
                         net (fo=1, routed)           0.114     1.173    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7_n_0
    SLICE_X114Y95        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.060     1.233 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.177     1.410    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     1.424 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.024     1.448    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.465ns  (logic 0.393ns (26.826%)  route 1.072ns (73.174%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[14])
                                                      0.285     0.285 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.809     1.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[14]
    SLICE_X112Y97        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.022     1.116 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_32/O
                         net (fo=1, routed)           0.088     1.204    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_32_n_0
    SLICE_X112Y97        LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.050     1.254 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_16/O
                         net (fo=1, routed)           0.092     1.346    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_16_n_0
    SLICE_X112Y94        LUT5 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.014     1.360 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.057     1.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.022     1.439 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     1.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.469ns  (logic 0.380ns (25.868%)  route 1.089ns (74.132%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.701ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.472ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[8])
                                                      0.237     0.237 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.615     0.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[8]
    SLICE_X117Y99        LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.060     0.912 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28/O
                         net (fo=1, routed)           0.095     1.007    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_28_n_0
    SLICE_X115Y99        LUT5 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.015     1.022 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.052     1.074    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X114Y100       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.014     1.088 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.075     1.163    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X114Y98        LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.014     1.177 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.235     1.412    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.452 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.469    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
                            (rising edge-triggered cell HSADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.558ns  (logic 0.422ns (27.086%)  route 1.136ns (72.914%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        1.693ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.693ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.546ns (routing 0.472ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y3           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV2_MUX
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y3           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_STATUS_COMMON[13])
                                                      0.241     0.241 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.638     0.879    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc3_common_stat[13]
    SLICE_X116Y98        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     0.914 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_59/O
                         net (fo=1, routed)           0.031     0.945    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_59_n_0
    SLICE_X116Y98        LUT5 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.060     1.005 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_43/O
                         net (fo=1, routed)           0.024     1.029    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_43_n_0
    SLICE_X116Y98        LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.023     1.052 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.154     1.206    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X115Y93        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.022     1.228 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6/O
                         net (fo=1, routed)           0.273     1.501    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_6_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.041     1.542 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.558    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.546     1.693    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.269ns  (logic 1.077ns (25.228%)  route 3.192ns (74.772%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.727     2.506    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[14]
    SLICE_X109Y105       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.051     2.557 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_23/O
                         net (fo=1, routed)           0.568     3.125    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_23_n_0
    SLICE_X105Y103       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098     3.223 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10/O
                         net (fo=1, routed)           0.091     3.314    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10_n_0
    SLICE_X105Y103       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     3.364 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.734     4.098    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     4.197 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     4.269    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.036ns  (logic 1.167ns (28.915%)  route 2.869ns (71.085%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           2.049     2.808    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[12]
    SLICE_X105Y101       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.149     2.957 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_48/O
                         net (fo=1, routed)           0.150     3.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_48_n_0
    SLICE_X103Y101       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     3.146 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22/O
                         net (fo=1, routed)           0.154     3.300    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22_n_0
    SLICE_X103Y102       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.098     3.398 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.444     3.842    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.122     3.964 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.072     4.036    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.956ns  (logic 1.115ns (28.185%)  route 2.841ns (71.815%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.734     2.574    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[15]
    SLICE_X108Y103       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     2.624 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_30/O
                         net (fo=1, routed)           0.414     3.038    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_30_n_0
    SLICE_X106Y103       LUT5 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.051     3.089 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.084     3.173    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X106Y104       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.051     3.224 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.543     3.767    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     3.890 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     3.956    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.624ns  (logic 1.283ns (35.403%)  route 2.341ns (64.597%))
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        2.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.418ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.236ns (routing 0.703ns, distribution 1.533ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.682     2.741    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[13]
    SLICE_X109Y105       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     2.831 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.519     3.350    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X105Y102       LUT4 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.098     3.448 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.091     3.539    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.036     3.575 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     3.624    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.236     2.418    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.546ns  (logic 0.925ns (26.086%)  route 2.621ns (73.914%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.475ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.475ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.293ns (routing 0.703ns, distribution 1.590ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.854     2.528    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[9]
    SLICE_X107Y105       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.037     2.565 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_24/O
                         net (fo=1, routed)           0.041     2.606    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_24_n_0
    SLICE_X107Y105       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     2.658 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7/O
                         net (fo=1, routed)           0.149     2.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7_n_0
    SLICE_X107Y101       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.125     2.932 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.505     3.437    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.474 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.072     3.546    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.293     2.475    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.285ns  (logic 1.117ns (34.003%)  route 2.168ns (65.997%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.745     2.498    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[10]
    SLICE_X109Y105       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.152     2.650 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.099     2.749    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X108Y105       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.124     2.873 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.252     3.125    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.088     3.213 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.072     3.285    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.139ns  (logic 0.928ns (29.564%)  route 2.211ns (70.436%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.703ns, distribution 1.546ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.855     2.586    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[8]
    SLICE_X107Y105       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.037     2.623 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12/O
                         net (fo=1, routed)           0.094     2.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12_n_0
    SLICE_X107Y105       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.037     2.754 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.212     2.966    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.123     3.089 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     3.139    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.876ns  (logic 0.911ns (31.676%)  route 1.965ns (68.324%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.671     2.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[11]
    SLICE_X108Y105       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     2.459 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.039     2.498    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X108Y105       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     2.533 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.189     2.722    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.088     2.810 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.066     2.876    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.412ns  (logic 0.430ns (30.453%)  route 0.982ns (69.547%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.841     1.208    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[11]
    SLICE_X108Y105       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.014     1.222 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.021     1.243    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X108Y105       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.014     1.257 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.096     1.353    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.035     1.388 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.024     1.412    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.565ns  (logic 0.460ns (29.393%)  route 1.105ns (70.607%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.701ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.472ns, distribution 1.082ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.935     1.317    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[8]
    SLICE_X107Y105       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.014     1.331 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12/O
                         net (fo=1, routed)           0.044     1.375    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_12_n_0
    SLICE_X107Y105       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     1.389 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.109     1.498    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     1.548 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.565    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.599ns  (logic 0.521ns (32.583%)  route 1.078ns (67.417%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.877     1.252    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[10]
    SLICE_X109Y105       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.061     1.313 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.051     1.364    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X108Y105       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.050     1.414 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.124     1.538    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.035     1.573 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.026     1.599    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.744ns  (logic 0.439ns (25.172%)  route 1.305ns (74.828%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.732ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.732ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.934     1.272    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[9]
    SLICE_X107Y105       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.014     1.286 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_24/O
                         net (fo=1, routed)           0.023     1.309    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_24_n_0
    SLICE_X107Y105       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.022     1.331 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7/O
                         net (fo=1, routed)           0.081     1.412    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7_n_0
    SLICE_X107Y101       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.051     1.463 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.241     1.704    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     1.718 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.026     1.744    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.798ns  (logic 0.614ns (34.149%)  route 1.184ns (65.851%))
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        1.693ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.693ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.546ns (routing 0.472ns, distribution 1.074ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.844     1.368    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[13]
    SLICE_X109Y105       LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.035     1.403 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.276     1.679    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X105Y102       LUT4 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.041     1.720 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.048     1.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.014     1.782 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     1.798    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.546     1.693    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.942ns  (logic 0.530ns (27.291%)  route 1.412ns (72.709%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.871     1.284    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[15]
    SLICE_X108Y103       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     1.306 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_30/O
                         net (fo=1, routed)           0.192     1.498    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_30_n_0
    SLICE_X106Y103       LUT5 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.022     1.520 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.047     1.567    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X106Y104       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.023     1.590 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.278     1.868    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.050     1.918 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     1.942    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.006ns  (logic 0.551ns (27.468%)  route 1.455ns (72.532%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.737ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.737ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.590ns (routing 0.472ns, distribution 1.118ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.036     1.422    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[12]
    SLICE_X105Y101       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.060     1.482 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_48/O
                         net (fo=1, routed)           0.079     1.561    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_48_n_0
    SLICE_X103Y101       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     1.576 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22/O
                         net (fo=1, routed)           0.078     1.654    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22_n_0
    SLICE_X103Y102       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.040     1.694 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.236     1.930    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.050     1.980 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.026     2.006    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.590     1.737    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.115ns  (logic 0.524ns (24.775%)  route 1.591ns (75.225%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.867     1.265    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[14]
    SLICE_X109Y105       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.022     1.287 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_23/O
                         net (fo=1, routed)           0.277     1.564    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_23_n_0
    SLICE_X105Y103       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.041     1.605 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10/O
                         net (fo=1, routed)           0.044     1.649    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_10_n_0
    SLICE_X105Y103       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.022     1.671 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.377     2.048    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.041     2.089 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     2.115    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_pl_0

Max Delay             9 Endpoints
Min Delay             9 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.986ns  (logic 0.107ns (3.583%)  route 2.879ns (96.417%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.867ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.438ns
    Source Clock Delay      (SCD):    3.305ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.632ns (routing 1.446ns, distribution 1.186ns)
  Clock Net Delay (Destination): 2.256ns (routing 0.703ns, distribution 1.553ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.632     3.305    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.384 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.339     4.723    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.751 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        1.540     6.291    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X107Y120       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.256     2.438    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X107Y120       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.148ns  (logic 1.074ns (20.862%)  route 4.074ns (79.138%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           2.508     3.287    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[14]
    SLICE_X108Y106       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     3.323 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.437     3.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X104Y106       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.125     3.885 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.323     4.208    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X105Y103       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     4.243 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.734     4.977    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     5.076 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.072     5.148    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.057ns  (logic 1.218ns (24.085%)  route 3.839ns (75.915%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.840     0.840 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           2.860     3.700    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[15]
    SLICE_X102Y106       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.122     3.822 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_26/O
                         net (fo=1, routed)           0.093     3.915    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_26_n_0
    SLICE_X102Y104       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.097     4.012 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.277     4.289    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X106Y104       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.036     4.325 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.543     4.868    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     4.991 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.066     5.057    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.961ns  (logic 1.112ns (22.415%)  route 3.849ns (77.585%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           2.157     2.910    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[11]
    SLICE_X108Y106       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.123     3.033 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_28/O
                         net (fo=1, routed)           0.599     3.632    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_28_n_0
    SLICE_X103Y104       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.149     3.781 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_16/O
                         net (fo=1, routed)           0.399     4.180    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_16_n_0
    SLICE_X105Y107       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     4.216 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.628     4.844    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.051     4.895 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.066     4.961    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.420ns  (logic 0.928ns (20.995%)  route 3.492ns (79.005%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        2.475ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.475ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.293ns (routing 0.703ns, distribution 1.590ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.674     0.674 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           2.160     2.834    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[9]
    SLICE_X108Y106       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.089     2.923 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21/O
                         net (fo=1, routed)           0.507     3.430    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21_n_0
    SLICE_X105Y105       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.089     3.519 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.248     3.767    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X107Y101       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     3.806 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.505     4.311    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     4.348 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.072     4.420    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.293     2.475    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.170ns  (logic 1.057ns (25.348%)  route 3.113ns (74.652%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.476ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.759     0.759 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           2.418     3.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[12]
    SLICE_X103Y103       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.037     3.214 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_47/O
                         net (fo=1, routed)           0.092     3.306    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_47_n_0
    SLICE_X103Y101       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.088     3.394 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.087     3.481    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X103Y102       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.051     3.532 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.444     3.976    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.122     4.098 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.072     4.170    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.130ns  (logic 1.325ns (32.082%)  route 2.805ns (67.918%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.418ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.236ns (routing 0.703ns, distribution 1.533ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      1.059     1.059 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           2.478     3.537    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[13]
    SLICE_X104Y106       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.051     3.588 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34/O
                         net (fo=1, routed)           0.040     3.628    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34_n_0
    SLICE_X104Y106       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.037     3.665 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.084     3.749    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X105Y106       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.089     3.838 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.154     3.992    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.089     4.081 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.049     4.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.236     2.418    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.120ns  (logic 0.987ns (23.956%)  route 3.133ns (76.044%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.473ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.473ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.753     0.753 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           2.472     3.225    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[10]
    SLICE_X105Y106       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.148     3.373 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9/O
                         net (fo=1, routed)           0.039     3.412    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9_n_0
    SLICE_X105Y106       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     3.447 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.550     3.997    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.051     4.048 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.072     4.120    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.853ns  (logic 0.962ns (24.968%)  route 2.891ns (75.032%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.431ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.431ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.249ns (routing 0.703ns, distribution 1.546ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.731     0.731 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           2.461     3.192    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[8]
    SLICE_X105Y106       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     3.338 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/O
                         net (fo=1, routed)           0.084     3.422    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14_n_0
    SLICE_X105Y107       LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.050     3.472 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.296     3.768    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     3.803 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     3.853    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.249     2.431    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.947ns  (logic 0.477ns (24.499%)  route 1.470ns (75.501%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.701ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.554ns (routing 0.472ns, distribution 1.082ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.251     1.633    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[8]
    SLICE_X105Y106       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.059     1.692 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14/O
                         net (fo=1, routed)           0.047     1.739    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_14_n_0
    SLICE_X105Y107       LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.022     1.761 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.155     1.916    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X106Y100       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     1.930 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.947    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.044ns  (logic 0.630ns (30.822%)  route 1.414ns (69.178%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.693ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.693ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.546ns (routing 0.472ns, distribution 1.074ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.524     0.524 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.251     1.775    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[13]
    SLICE_X104Y106       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.022     1.797 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34/O
                         net (fo=1, routed)           0.022     1.819    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_34_n_0
    SLICE_X104Y106       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.014     1.833 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.043     1.876    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X105Y106       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.035     1.911 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.082     1.993    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X105Y100       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.035     2.028 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.016     2.044    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.546     1.693    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y100       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.049ns  (logic 0.470ns (22.938%)  route 1.579ns (77.062%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.375     0.375 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.251     1.626    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[10]
    SLICE_X105Y106       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.059     1.685 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9/O
                         net (fo=1, routed)           0.021     1.706    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_9_n_0
    SLICE_X105Y106       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.014     1.720 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.281     2.001    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X109Y102       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.022     2.023 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.026     2.049    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.099ns  (logic 0.507ns (24.154%)  route 1.592ns (75.846%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.737ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.737ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.590ns (routing 0.472ns, distribution 1.118ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.386     0.386 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.235     1.621    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[12]
    SLICE_X103Y103       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     1.635 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_47/O
                         net (fo=1, routed)           0.048     1.683    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_47_n_0
    SLICE_X103Y101       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.035     1.718 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21/O
                         net (fo=1, routed)           0.047     1.765    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_21_n_0
    SLICE_X103Y102       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.022     1.787 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.236     2.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X110Y97        LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.050     2.073 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.026     2.099    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.590     1.737    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.170ns  (logic 0.437ns (20.138%)  route 1.733ns (79.862%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Path Skew:        1.732ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.732ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.338     0.338 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.089     1.427    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[9]
    SLICE_X108Y106       LUT5 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     1.462 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21/O
                         net (fo=1, routed)           0.246     1.708    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21_n_0
    SLICE_X105Y105       LUT5 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.035     1.743 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.131     1.874    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X107Y101       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.015     1.889 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.241     2.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X112Y99        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     2.144 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.026     2.170    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X112Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.419ns  (logic 0.514ns (21.248%)  route 1.905ns (78.752%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.731ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.731ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.584ns (routing 0.472ns, distribution 1.112ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.367     0.367 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.098     1.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[11]
    SLICE_X108Y106       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.515 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_28/O
                         net (fo=1, routed)           0.293     1.808    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_28_n_0
    SLICE_X103Y104       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.060     1.868 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_16/O
                         net (fo=1, routed)           0.183     2.051    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_16_n_0
    SLICE_X105Y107       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.015     2.066 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.307     2.373    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X109Y102       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.022     2.395 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.024     2.419    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.584     1.731    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X109Y102       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.509ns  (logic 0.568ns (22.638%)  route 1.941ns (77.361%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.448     1.861    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[15]
    SLICE_X102Y106       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.050     1.911 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_26/O
                         net (fo=1, routed)           0.050     1.961    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_26_n_0
    SLICE_X102Y104       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.040     2.001 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.141     2.142    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X106Y104       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.015     2.157 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.278     2.435    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X113Y94        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.050     2.485 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.024     2.509    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell HSDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.591ns  (logic 0.519ns (20.031%)  route 2.072ns (79.969%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.733ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.733ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.398     0.398 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.274     1.672    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[14]
    SLICE_X108Y106       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     1.687 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21/O
                         net (fo=1, routed)           0.227     1.914    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_21_n_0
    SLICE_X104Y106       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.051     1.965 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.168     2.133    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X105Y103       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.014     2.147 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.377     2.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X113Y94        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.041     2.565 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.026     2.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y94        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.586ns  (logic 0.056ns (3.531%)  route 1.530ns (96.469%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.076ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.701ns
    Source Clock Delay      (SCD):    1.778ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.429ns (routing 0.779ns, distribution 0.650ns)
  Clock Net Delay (Destination): 1.554ns (routing 0.472ns, distribution 1.082ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.429     1.778    d_1_i/rst_dac0/U0/slowest_sync_clk
    SLICE_X51Y264        FDRE                                         r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y264        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.817 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.709     2.526    d_1_i/rst_dac0/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.543 r  d_1_i/rst_dac0/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=7908, routed)        0.821     3.364    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X107Y120       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.554     1.701    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X107Y120       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  clk_pl_0

Max Delay           136 Endpoints
Min Delay           136 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.767ns  (logic 0.770ns (27.828%)  route 1.997ns (72.172%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        -4.375ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.427ns
    Source Clock Delay      (SCD):    6.802ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.300ns (routing 1.562ns, distribution 1.738ns)
  Clock Net Delay (Destination): 2.245ns (routing 0.703ns, distribution 1.542ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.300     6.802    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.450     7.252 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           0.979     8.231    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[5]
    SLICE_X115Y92        LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.088     8.319 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25/O
                         net (fo=1, routed)           0.340     8.659    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25_n_0
    SLICE_X115Y92        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.145     8.804 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14/O
                         net (fo=1, routed)           0.149     8.953    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14_n_0
    SLICE_X115Y97        LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.037     8.990 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4/O
                         net (fo=1, routed)           0.480     9.470    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4_n_0
    SLICE_X106Y97        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.050     9.520 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.049     9.569    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.245     2.427    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.432ns  (logic 0.079ns (3.248%)  route 2.353ns (96.752%))
  Logic Levels:           0  
  Clock Path Skew:        -4.015ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.476ns
    Source Clock Delay      (SCD):    6.491ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.989ns (routing 1.562ns, distribution 1.427ns)
  Clock Net Delay (Destination): 2.294ns (routing 0.703ns, distribution 1.591ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.989     6.491    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X55Y209        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y209        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     6.570 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           2.353     8.923    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X111Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.294     2.476    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X111Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.636ns  (logic 0.081ns (4.950%)  route 1.555ns (95.050%))
  Logic Levels:           0  
  Clock Path Skew:        -4.201ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.231ns
    Source Clock Delay      (SCD):    6.432ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.930ns (routing 1.562ns, distribution 1.368ns)
  Clock Net Delay (Destination): 2.049ns (routing 0.703ns, distribution 1.346ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.930     6.432    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X80Y209        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y209        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     6.513 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           1.555     8.068    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X79Y136        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.049     2.231    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X79Y136        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.660ns  (logic 0.079ns (11.964%)  route 0.581ns (88.036%))
  Logic Levels:           0  
  Clock Path Skew:        -4.171ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.314ns
    Source Clock Delay      (SCD):    6.485ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      2.983ns (routing 1.562ns, distribution 1.421ns)
  Clock Net Delay (Destination): 2.132ns (routing 0.703ns, distribution 1.429ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.983     6.485    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X76Y114        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y114        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     6.564 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.581     7.145    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X81Y110        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.132     2.314    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X81Y110        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.624ns  (logic 0.307ns (18.904%)  route 1.317ns (81.096%))
  Logic Levels:           0  
  Clock Path Skew:        -4.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.170ns
    Source Clock Delay      (SCD):    6.580ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.078ns (routing 1.562ns, distribution 1.516ns)
  Clock Net Delay (Destination): 1.988ns (routing 0.703ns, distribution 1.285ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.078     6.580    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X82Y151        RAMD32                                       r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y151        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     6.887 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB_D1/O
                         net (fo=1, routed)           1.317     8.204    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[3]
    SLICE_X68Y180        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.988     2.170    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X68Y180        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.500ns  (logic 0.292ns (19.467%)  route 1.208ns (80.533%))
  Logic Levels:           0  
  Clock Path Skew:        -4.388ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.192ns
    Source Clock Delay      (SCD):    6.580ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.078ns (routing 1.562ns, distribution 1.516ns)
  Clock Net Delay (Destination): 2.010ns (routing 0.703ns, distribution 1.307ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.078     6.580    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X82Y151        RAMD32                                       r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y151        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     6.872 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMB/O
                         net (fo=1, routed)           1.208     8.080    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[2]
    SLICE_X71Y164        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.010     2.192    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X71Y164        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.488ns  (logic 0.281ns (18.884%)  route 1.207ns (81.116%))
  Logic Levels:           0  
  Clock Path Skew:        -4.386ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.192ns
    Source Clock Delay      (SCD):    6.578ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.076ns (routing 1.562ns, distribution 1.514ns)
  Clock Net Delay (Destination): 2.010ns (routing 0.703ns, distribution 1.307ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.076     6.578    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/WCLK
    SLICE_X82Y150        RAMD32                                       r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y150        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281     6.859 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMG/O
                         net (fo=1, routed)           1.207     8.066    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[26]
    SLICE_X73Y164        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.010     2.192    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X73Y164        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[26]/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[35]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.427ns  (logic 0.301ns (21.093%)  route 1.126ns (78.907%))
  Logic Levels:           0  
  Clock Path Skew:        -4.389ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.195ns
    Source Clock Delay      (SCD):    6.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.082ns (routing 1.562ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.013ns (routing 0.703ns, distribution 1.310ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.082     6.584    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/WCLK
    SLICE_X82Y154        RAMD32                                       r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y154        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     6.885 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMD_D1/O
                         net (fo=1, routed)           1.126     8.011    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[35]
    SLICE_X71Y177        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[35]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.013     2.195    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X71Y177        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[35]/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.415ns  (logic 0.289ns (20.424%)  route 1.126ns (79.576%))
  Logic Levels:           0  
  Clock Path Skew:        -4.388ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.196ns
    Source Clock Delay      (SCD):    6.584ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.082ns (routing 1.562ns, distribution 1.520ns)
  Clock Net Delay (Destination): 2.014ns (routing 0.703ns, distribution 1.311ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.082     6.584    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/WCLK
    SLICE_X82Y154        RAMD32                                       r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y154        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     6.873 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_28_41/RAMA/O
                         net (fo=1, routed)           1.126     7.999    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[28]
    SLICE_X72Y180        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.014     2.196    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X72Y180        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.414ns  (logic 0.295ns (20.863%)  route 1.119ns (79.137%))
  Logic Levels:           0  
  Clock Path Skew:        -4.385ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.195ns
    Source Clock Delay      (SCD):    6.580ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      3.078ns (routing 1.562ns, distribution 1.516ns)
  Clock Net Delay (Destination): 2.013ns (routing 0.703ns, distribution 1.310ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.078     6.580    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/WCLK
    SLICE_X82Y151        RAMD32                                       r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y151        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     6.875 r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_0_13/RAMF/O
                         net (fo=1, routed)           1.119     7.994    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[10]
    SLICE_X71Y177        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.013     2.195    d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X71Y177        FDRE                                         r  d_1_i/axis_weighted_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.314ns  (logic 0.039ns (12.417%)  route 0.275ns (87.583%))
  Logic Levels:           0  
  Clock Path Skew:        -2.227ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.624ns
    Source Clock Delay      (SCD):    3.851ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.645ns (routing 0.858ns, distribution 0.787ns)
  Clock Net Delay (Destination): 1.477ns (routing 0.472ns, distribution 1.005ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.645     3.851    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X76Y114        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y114        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     3.890 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.275     4.165    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X81Y110        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.477     1.624    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X81Y110        FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.818ns  (logic 0.040ns (4.893%)  route 0.778ns (95.107%))
  Logic Levels:           0  
  Clock Path Skew:        -2.256ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.564ns
    Source Clock Delay      (SCD):    3.820ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.614ns (routing 0.858ns, distribution 0.756ns)
  Clock Net Delay (Destination): 1.417ns (routing 0.472ns, distribution 0.945ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.614     3.820    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X80Y209        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X80Y209        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     3.860 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.778     4.638    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X79Y136        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.417     1.564    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X79Y136        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.224ns  (logic 0.039ns (3.186%)  route 1.185ns (96.814%))
  Logic Levels:           0  
  Clock Path Skew:        -2.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.732ns
    Source Clock Delay      (SCD):    3.848ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.642ns (routing 0.858ns, distribution 0.784ns)
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.642     3.848    d_1_i/rst_adc0_x2/U0/slowest_sync_clk
    SLICE_X55Y209        FDRE                                         r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y209        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     3.887 r  d_1_i/rst_adc0_x2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.185     5.072    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/src_in
    SLICE_X111Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/dest_clk
    SLICE_X111Y106       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
                            (rising edge-triggered cell HSADC clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.370ns  (logic 0.358ns (26.131%)  route 1.012ns (73.869%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        -2.312ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.699ns
    Source Clock Delay      (SCD):    4.011ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.805ns (routing 0.858ns, distribution 0.947ns)
  Clock Net Delay (Destination): 1.552ns (routing 0.472ns, distribution 1.080ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.805     4.011    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m0_axis_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y0           HSADC (Prop_HSADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.228     4.239 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           0.481     4.720    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_15_0[5]
    SLICE_X115Y92        LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.035     4.755 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25/O
                         net (fo=1, routed)           0.176     4.931    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_25_n_0
    SLICE_X115Y92        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.059     4.990 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14/O
                         net (fo=1, routed)           0.081     5.071    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_14_n_0
    SLICE_X115Y97        LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.014     5.085 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4/O
                         net (fo=1, routed)           0.258     5.343    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_4_n_0
    SLICE_X106Y97        LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.022     5.365 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.016     5.381    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.552     1.699    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.039ns (21.637%)  route 0.141ns (78.363%))
  Logic Levels:           0  
  Clock Path Skew:        -2.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.446ns
    Source Clock Delay      (SCD):    3.843ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.637ns (routing 0.858ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.299ns (routing 0.472ns, distribution 0.827ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.637     3.843    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X56Y213        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y213        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     3.882 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_reg[1]/Q
                         net (fo=83, routed)          0.141     4.023    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/Q[1]
    SLICE_X55Y213        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.299     1.446    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X55Y213        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[45]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.168ns  (logic 0.110ns (65.476%)  route 0.058ns (34.524%))
  Logic Levels:           0  
  Clock Path Skew:        -2.413ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.445ns
    Source Clock Delay      (SCD):    3.858ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.652ns (routing 0.858ns, distribution 0.794ns)
  Clock Net Delay (Destination): 1.298ns (routing 0.472ns, distribution 0.826ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.652     3.858    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/WCLK
    SLICE_X56Y206        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y206        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.110     3.968 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMB_D1/O
                         net (fo=1, routed)           0.058     4.026    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[45]
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[45]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.298     1.445    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[45]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.168ns  (logic 0.111ns (66.071%)  route 0.057ns (33.929%))
  Logic Levels:           0  
  Clock Path Skew:        -2.414ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.458ns
    Source Clock Delay      (SCD):    3.872ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.666ns (routing 0.858ns, distribution 0.808ns)
  Clock Net Delay (Destination): 1.311ns (routing 0.472ns, distribution 0.839ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.666     3.872    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/WCLK
    SLICE_X48Y213        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y213        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.983 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_14_27/RAMF_D1/O
                         net (fo=1, routed)           0.057     4.040    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[25]
    SLICE_X47Y213        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.311     1.458    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X47Y213        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[25]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[53]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.189ns  (logic 0.111ns (58.730%)  route 0.078ns (41.270%))
  Logic Levels:           0  
  Clock Path Skew:        -2.413ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.445ns
    Source Clock Delay      (SCD):    3.858ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.652ns (routing 0.858ns, distribution 0.794ns)
  Clock Net Delay (Destination): 1.298ns (routing 0.472ns, distribution 0.826ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.652     3.858    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/WCLK
    SLICE_X56Y206        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y206        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.969 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMF_D1/O
                         net (fo=1, routed)           0.078     4.047    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[53]
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[53]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.298     1.445    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[53]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[43]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.195ns  (logic 0.111ns (56.923%)  route 0.084ns (43.077%))
  Logic Levels:           0  
  Clock Path Skew:        -2.413ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.445ns
    Source Clock Delay      (SCD):    3.858ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.652ns (routing 0.858ns, distribution 0.794ns)
  Clock Net Delay (Destination): 1.298ns (routing 0.472ns, distribution 0.826ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.652     3.858    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/WCLK
    SLICE_X56Y206        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y206        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     3.969 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_42_55/RAMA_D1/O
                         net (fo=1, routed)           0.084     4.053    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[43]
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[43]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.298     1.445    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X55Y206        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[43]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[57]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.197ns  (logic 0.111ns (56.345%)  route 0.086ns (43.655%))
  Logic Levels:           0  
  Clock Path Skew:        -2.421ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.439ns
    Source Clock Delay      (SCD):    3.860ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.243ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.323ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Source):      1.654ns (routing 0.858ns, distribution 0.796ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.472ns, distribution 0.820ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.654     3.860    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/WCLK
    SLICE_X56Y208        RAMD32                                       r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y208        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     3.971 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/RAM_reg_0_3_56_63/RAMA_D1/O
                         net (fo=1, routed)           0.086     4.057    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob0__0[57]
    SLICE_X55Y208        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[57]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.292     1.439    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X55Y208        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/fifo_i/mem_i/dob_reg[57]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_pl_0

Max Delay          1745 Endpoints
Min Delay          1745 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.966ns  (logic 0.130ns (13.454%)  route 0.836ns (86.546%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.160ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.186ns
    Source Clock Delay      (SCD):    5.346ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.731ns (routing 1.611ns, distribution 1.120ns)
  Clock Net Delay (Destination): 2.004ns (routing 0.703ns, distribution 1.301ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.731     5.346    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y216        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y216        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.425 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.533     5.958    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X68Y191        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     6.009 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.303     6.312    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X73Y191        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.004     2.186    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X73Y191        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.337ns  (logic 0.079ns (23.426%)  route 0.258ns (76.574%))
  Logic Levels:           0  
  Clock Path Skew:        -3.275ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.186ns
    Source Clock Delay      (SCD):    5.461ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.846ns (routing 1.611ns, distribution 1.235ns)
  Clock Net Delay (Destination): 2.004ns (routing 0.703ns, distribution 1.301ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.846     5.461    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X74Y190        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y190        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     5.540 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.258     5.798    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X73Y191        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.004     2.186    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X73Y191        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.425ns  (logic 0.178ns (41.879%)  route 0.247ns (58.121%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -3.288ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.058ns
    Source Clock Delay      (SCD):    5.346ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.731ns (routing 1.611ns, distribution 1.120ns)
  Clock Net Delay (Destination): 1.876ns (routing 0.703ns, distribution 1.173ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.731     5.346    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y216        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y216        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     5.425 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.100     5.525    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X57Y216        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.099     5.624 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.147     5.771    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X57Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.876     2.058    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X57Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.292ns  (logic 0.079ns (27.045%)  route 0.213ns (72.955%))
  Logic Levels:           0  
  Clock Path Skew:        -3.282ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.057ns
    Source Clock Delay      (SCD):    5.339ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.724ns (routing 1.611ns, distribution 1.113ns)
  Clock Net Delay (Destination): 1.875ns (routing 0.703ns, distribution 1.172ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.724     5.339    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X55Y215        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y215        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     5.418 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.213     5.631    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X55Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.875     2.057    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X55Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/ADDRARDADDR[3]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.710ns  (logic 0.228ns (6.146%)  route 3.482ns (93.854%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -3.091ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.259ns
    Source Clock Delay      (SCD):    5.350ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.735ns (routing 1.611ns, distribution 1.124ns)
  Clock Net Delay (Destination): 2.077ns (routing 0.703ns, distribution 1.374ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.735     5.350    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X44Y194        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y194        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.429 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/Q
                         net (fo=27, routed)          0.374     5.803    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[0]
    SLICE_X42Y191        LUT5 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.952 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_12/O
                         net (fo=28, routed)          3.108     9.060    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[0]
    RAMB36_X7Y52         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/ADDRARDADDR[3]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.077     2.259    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y52         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_10/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/ADDRARDADDR[3]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.645ns  (logic 0.228ns (6.255%)  route 3.417ns (93.745%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -3.098ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.252ns
    Source Clock Delay      (SCD):    5.350ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.735ns (routing 1.611ns, distribution 1.124ns)
  Clock Net Delay (Destination): 2.070ns (routing 0.703ns, distribution 1.367ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.735     5.350    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X44Y194        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y194        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.429 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/Q
                         net (fo=27, routed)          0.374     5.803    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[0]
    SLICE_X42Y191        LUT5 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.952 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_12/O
                         net (fo=28, routed)          3.043     8.995    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[0]
    RAMB36_X7Y53         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/ADDRARDADDR[3]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.070     2.252    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y53         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_11/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/ADDRARDADDR[4]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.524ns  (logic 0.228ns (6.470%)  route 3.296ns (93.530%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -3.080ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.270ns
    Source Clock Delay      (SCD):    5.350ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.735ns (routing 1.611ns, distribution 1.124ns)
  Clock Net Delay (Destination): 2.088ns (routing 0.703ns, distribution 1.385ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.735     5.350    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X44Y194        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y194        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.429 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/Q
                         net (fo=27, routed)          0.374     5.803    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[0]
    SLICE_X42Y191        LUT5 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.952 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_12/O
                         net (fo=28, routed)          2.922     8.874    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[0]
    RAMB36_X7Y49         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/ADDRARDADDR[4]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.088     2.270    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y49         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_7/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/ADDRARDADDR[3]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.511ns  (logic 0.228ns (6.494%)  route 3.283ns (93.506%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -3.086ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.264ns
    Source Clock Delay      (SCD):    5.350ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.735ns (routing 1.611ns, distribution 1.124ns)
  Clock Net Delay (Destination): 2.082ns (routing 0.703ns, distribution 1.379ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.735     5.350    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X44Y194        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y194        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.429 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/Q
                         net (fo=27, routed)          0.374     5.803    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[0]
    SLICE_X42Y191        LUT5 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.952 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_12/O
                         net (fo=28, routed)          2.909     8.861    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[0]
    RAMB36_X7Y51         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/ADDRARDADDR[3]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.082     2.264    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y51         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_9/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/ADDRARDADDR[3]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.467ns  (logic 0.228ns (6.576%)  route 3.239ns (93.424%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -3.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.268ns
    Source Clock Delay      (SCD):    5.350ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.735ns (routing 1.611ns, distribution 1.124ns)
  Clock Net Delay (Destination): 2.086ns (routing 0.703ns, distribution 1.383ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.735     5.350    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X44Y194        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y194        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.429 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/Q
                         net (fo=27, routed)          0.374     5.803    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[0]
    SLICE_X42Y191        LUT5 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.952 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_12/O
                         net (fo=28, routed)          2.865     8.817    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[0]
    RAMB36_X7Y50         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/ADDRARDADDR[3]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.086     2.268    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X7Y50         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_8/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_12/ADDRARDADDR[2]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.438ns  (logic 0.228ns (6.633%)  route 3.210ns (93.367%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        -3.244ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.106ns
    Source Clock Delay      (SCD):    5.350ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.735ns (routing 1.611ns, distribution 1.124ns)
  Clock Net Delay (Destination): 1.924ns (routing 0.703ns, distribution 1.221ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.243     2.469    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.342 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.587    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.615 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.735     5.350    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X44Y194        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y194        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     5.429 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[1]/Q
                         net (fo=27, routed)          0.374     5.803    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_12[0]
    SLICE_X42Y191        LUT5 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.149     5.952 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/axis_read_i/RAM_reg_bram_0_i_12/O
                         net (fo=28, routed)          2.835     8.788    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ext_mem_addr[0]
    RAMB36_X5Y46         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_12/ADDRARDADDR[2]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.924     2.106    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/ps_clk_i
    RAMB36_X5Y46         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_12/CLKARDCLK





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.231%)  route 0.082ns (67.769%))
  Logic Levels:           0  
  Clock Path Skew:        -1.785ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.445ns
    Source Clock Delay      (SCD):    3.230ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.490ns (routing 0.877ns, distribution 0.613ns)
  Clock Net Delay (Destination): 1.298ns (routing 0.472ns, distribution 0.826ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.490     3.230    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y212        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     3.269 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.082     3.351    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.298     1.445    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.041ns (33.064%)  route 0.083ns (66.935%))
  Logic Levels:           0  
  Clock Path Skew:        -1.785ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.445ns
    Source Clock Delay      (SCD):    3.230ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.490ns (routing 0.877ns, distribution 0.613ns)
  Clock Net Delay (Destination): 1.298ns (routing 0.472ns, distribution 0.826ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.490     3.230    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y212        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.271 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.083     3.354    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.298     1.445    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.697%)  route 0.088ns (69.303%))
  Logic Levels:           0  
  Clock Path Skew:        -1.792ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.440ns
    Source Clock Delay      (SCD):    3.232ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.492ns (routing 0.877ns, distribution 0.615ns)
  Clock Net Delay (Destination): 1.293ns (routing 0.472ns, distribution 0.821ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.492     3.232    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X55Y215        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y215        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.271 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.088     3.359    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X55Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.293     1.440    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X55Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.040ns (29.197%)  route 0.097ns (70.803%))
  Logic Levels:           0  
  Clock Path Skew:        -1.774ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.456ns
    Source Clock Delay      (SCD):    3.230ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.490ns (routing 0.877ns, distribution 0.613ns)
  Clock Net Delay (Destination): 1.309ns (routing 0.472ns, distribution 0.837ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.490     3.230    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y212        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     3.270 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.097     3.367    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.309     1.456    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.149ns  (logic 0.039ns (26.175%)  route 0.110ns (73.826%))
  Logic Levels:           0  
  Clock Path Skew:        -1.783ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.444ns
    Source Clock Delay      (SCD):    3.227ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.487ns (routing 0.877ns, distribution 0.610ns)
  Clock Net Delay (Destination): 1.297ns (routing 0.472ns, distribution 0.825ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.487     3.227    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y210        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.266 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.110     3.376    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.297     1.444    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X52Y210        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.039ns (22.543%)  route 0.134ns (77.457%))
  Logic Levels:           0  
  Clock Path Skew:        -1.774ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.456ns
    Source Clock Delay      (SCD):    3.230ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.490ns (routing 0.877ns, distribution 0.613ns)
  Clock Net Delay (Destination): 1.309ns (routing 0.472ns, distribution 0.837ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.490     3.230    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X55Y212        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y212        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     3.269 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.134     3.403    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.309     1.456    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X56Y214        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.039ns (32.773%)  route 0.080ns (67.227%))
  Logic Levels:           0  
  Clock Path Skew:        -1.768ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.520ns
    Source Clock Delay      (SCD):    3.288ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.548ns (routing 0.877ns, distribution 0.671ns)
  Clock Net Delay (Destination): 1.373ns (routing 0.472ns, distribution 0.901ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.548     3.288    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X68Y185        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y185        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     3.327 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.080     3.407    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X68Y185        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.373     1.520    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X68Y185        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.041ns (33.064%)  route 0.083ns (66.935%))
  Logic Levels:           0  
  Clock Path Skew:        -1.767ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.521ns
    Source Clock Delay      (SCD):    3.288ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.548ns (routing 0.877ns, distribution 0.671ns)
  Clock Net Delay (Destination): 1.374ns (routing 0.472ns, distribution 0.902ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.548     3.288    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X68Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y184        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     3.329 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.083     3.412    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X68Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.374     1.521    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X68Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.080ns (44.523%)  route 0.100ns (55.477%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -1.793ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.442ns
    Source Clock Delay      (SCD):    3.235ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.495ns (routing 0.877ns, distribution 0.618ns)
  Clock Net Delay (Destination): 1.295ns (routing 0.472ns, distribution 0.823ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.495     3.235    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X57Y216        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y216        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     3.274 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.052     3.326    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X57Y216        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.041     3.367 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.048     3.415    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X57Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.295     1.442    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X57Y216        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.146ns  (logic 0.039ns (26.712%)  route 0.107ns (73.288%))
  Logic Levels:           0  
  Clock Path Skew:        -1.778ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.513ns
    Source Clock Delay      (SCD):    3.291ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.551ns (routing 0.877ns, distribution 0.674ns)
  Clock Net Delay (Destination): 1.366ns (routing 0.472ns, distribution 0.894ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.227     1.347    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.577 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.723    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.740 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.551     3.291    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y182        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     3.330 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.107     3.437    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.366     1.513    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Max Delay           276 Endpoints
Min Delay           276 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        5.164ns  (logic 0.079ns (1.530%)  route 5.085ns (98.470%))
  Logic Levels:           0  
  Clock Path Skew:        -0.679ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.159ns
    Source Clock Delay      (SCD):    2.838ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.612ns (routing 0.777ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.977ns (routing 0.703ns, distribution 1.274ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.612     2.838    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.917 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         5.085     8.003    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X49Y56         FDCE                                         f  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.977     2.159    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X49Y56         FDCE                                         r  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        5.164ns  (logic 0.079ns (1.530%)  route 5.085ns (98.470%))
  Logic Levels:           0  
  Clock Path Skew:        -0.679ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.159ns
    Source Clock Delay      (SCD):    2.838ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.612ns (routing 0.777ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.977ns (routing 0.703ns, distribution 1.274ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.612     2.838    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.917 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         5.085     8.003    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X49Y56         FDCE                                         f  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.977     2.159    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X49Y56         FDCE                                         r  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        5.164ns  (logic 0.079ns (1.530%)  route 5.085ns (98.470%))
  Logic Levels:           0  
  Clock Path Skew:        -0.679ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.159ns
    Source Clock Delay      (SCD):    2.838ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.612ns (routing 0.777ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.977ns (routing 0.703ns, distribution 1.274ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.612     2.838    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.917 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         5.085     8.003    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X49Y56         FDCE                                         f  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.977     2.159    d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X49Y56         FDCE                                         r  d_1_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.363ns  (logic 0.077ns (1.436%)  route 5.286ns (98.564%))
  Logic Levels:           0  
  Clock Path Skew:        -0.462ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.136ns
    Source Clock Delay      (SCD):    2.598ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.372ns (routing 0.777ns, distribution 1.595ns)
  Clock Net Delay (Destination): 1.954ns (routing 0.703ns, distribution 1.251ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.372     2.598    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X90Y213        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y213        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.675 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=259, routed)         5.286     7.961    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X53Y14         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.954     2.136    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X53Y14         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        5.035ns  (logic 0.079ns (1.569%)  route 4.956ns (98.431%))
  Logic Levels:           0  
  Clock Path Skew:        -0.677ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.162ns
    Source Clock Delay      (SCD):    2.838ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.612ns (routing 0.777ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.980ns (routing 0.703ns, distribution 1.277ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.612     2.838    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.917 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         4.956     7.874    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X44Y58         FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.980     2.162    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X44Y58         FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        5.035ns  (logic 0.079ns (1.569%)  route 4.956ns (98.431%))
  Logic Levels:           0  
  Clock Path Skew:        -0.677ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.162ns
    Source Clock Delay      (SCD):    2.838ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.612ns (routing 0.777ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.980ns (routing 0.703ns, distribution 1.277ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.612     2.838    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.917 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         4.956     7.874    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X44Y58         FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.980     2.162    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X44Y58         FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        5.035ns  (logic 0.079ns (1.569%)  route 4.956ns (98.431%))
  Logic Levels:           0  
  Clock Path Skew:        -0.677ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.162ns
    Source Clock Delay      (SCD):    2.838ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.612ns (routing 0.777ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.980ns (routing 0.703ns, distribution 1.277ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.612     2.838    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.917 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         4.956     7.874    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X44Y58         FDCE                                         f  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.980     2.162    d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X44Y58         FDCE                                         r  d_1_i/axi_smc/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.237ns  (logic 0.077ns (1.470%)  route 5.160ns (98.530%))
  Logic Levels:           0  
  Clock Path Skew:        -0.445ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.153ns
    Source Clock Delay      (SCD):    2.598ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.372ns (routing 0.777ns, distribution 1.595ns)
  Clock Net Delay (Destination): 1.971ns (routing 0.703ns, distribution 1.268ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.372     2.598    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X90Y213        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y213        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.675 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=259, routed)         5.160     7.835    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X51Y8          FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.971     2.153    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X51Y8          FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.992ns  (logic 0.079ns (1.582%)  route 4.913ns (98.418%))
  Logic Levels:           0  
  Clock Path Skew:        -0.679ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.160ns
    Source Clock Delay      (SCD):    2.838ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.612ns (routing 0.777ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.978ns (routing 0.703ns, distribution 1.275ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.612     2.838    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.917 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         4.913     7.830    d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X38Y72         FDCE                                         f  d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.978     2.160    d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X38Y72         FDCE                                         r  d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.992ns  (logic 0.079ns (1.582%)  route 4.913ns (98.418%))
  Logic Levels:           0  
  Clock Path Skew:        -0.679ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.160ns
    Source Clock Delay      (SCD):    2.838ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.612ns (routing 0.777ns, distribution 1.835ns)
  Clock Net Delay (Destination): 1.978ns (routing 0.703ns, distribution 1.275ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.612     2.838    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.917 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         4.913     7.830    d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X38Y72         FDCE                                         f  d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.978     2.160    d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X38Y72         FDCE                                         r  d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.135ns  (logic 0.038ns (28.148%)  route 0.097ns (71.852%))
  Logic Levels:           0  
  Clock Path Skew:        0.190ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.556ns
    Source Clock Delay      (SCD):    1.367ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.247ns (routing 0.421ns, distribution 0.826ns)
  Clock Net Delay (Destination): 1.409ns (routing 0.472ns, distribution 0.937ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.247     1.367    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X69Y103        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y103        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.405 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.097     1.502    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X69Y103        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.409     1.556    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X69Y103        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.039ns (28.580%)  route 0.097ns (71.420%))
  Logic Levels:           0  
  Clock Path Skew:        0.195ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.572ns
    Source Clock Delay      (SCD):    1.377ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.421ns, distribution 0.836ns)
  Clock Net Delay (Destination): 1.425ns (routing 0.472ns, distribution 0.953ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.257     1.377    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X72Y99         FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y99         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.416 r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.097     1.513    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X72Y103        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.425     1.572    d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X72Y103        FDRE                                         r  d_1_i/axis_switch_buf/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.168%)  route 0.058ns (59.832%))
  Logic Levels:           0  
  Clock Path Skew:        0.186ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.621ns
    Source Clock Delay      (SCD):    1.435ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.315ns (routing 0.421ns, distribution 0.894ns)
  Clock Net Delay (Destination): 1.474ns (routing 0.472ns, distribution 1.002ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.315     1.435    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X0Y196         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X0Y196         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.474 r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.058     1.532    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X0Y195         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.474     1.621    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X0Y195         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        0.188ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.642ns
    Source Clock Delay      (SCD):    1.454ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.334ns (routing 0.421ns, distribution 0.913ns)
  Clock Net Delay (Destination): 1.495ns (routing 0.472ns, distribution 1.023ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.334     1.454    d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/s_axi_ctrl_aclk
    SLICE_X1Y191         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y191         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.493 r  d_1_i/axis_switch_gen/inst/gen_static_router.inst_static_router/inst_start_router_config/ctrl_soft_reset_r_reg/Q
                         net (fo=1, routed)           0.064     1.557    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/src_in
    SLICE_X1Y191         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.495     1.642    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/dest_clk
    SLICE_X1Y191         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_rst_synch/inst_xpm_cdc_single/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.039ns (30.073%)  route 0.091ns (69.927%))
  Logic Levels:           0  
  Clock Path Skew:        0.199ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.659ns
    Source Clock Delay      (SCD):    1.460ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.340ns (routing 0.421ns, distribution 0.919ns)
  Clock Net Delay (Destination): 1.512ns (routing 0.472ns, distribution 1.040ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.340     1.460    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X92Y76         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y76         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.499 r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.091     1.590    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X93Y75         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.512     1.659    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X93Y75         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.150ns  (logic 0.038ns (25.387%)  route 0.112ns (74.613%))
  Logic Levels:           0  
  Clock Path Skew:        0.175ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.620ns
    Source Clock Delay      (SCD):    1.445ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.325ns (routing 0.421ns, distribution 0.904ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.472ns, distribution 1.001ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.325     1.445    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X1Y194         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X1Y194         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.483 r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.112     1.594    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X0Y196         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.473     1.620    d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X0Y196         FDRE                                         r  d_1_i/axis_switch_gen/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.236ns  (logic 0.038ns (16.123%)  route 0.198ns (83.877%))
  Logic Levels:           0  
  Clock Path Skew:        0.193ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.652ns
    Source Clock Delay      (SCD):    1.460ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.340ns (routing 0.421ns, distribution 0.919ns)
  Clock Net Delay (Destination): 1.505ns (routing 0.472ns, distribution 1.033ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.340     1.460    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X93Y75         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y75         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.498 r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.198     1.695    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X92Y75         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.505     1.652    d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X92Y75         FDRE                                         r  d_1_i/axis_switch_avg/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.039ns (26.865%)  route 0.106ns (73.135%))
  Logic Levels:           0  
  Clock Path Skew:        0.214ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.768ns
    Source Clock Delay      (SCD):    1.555ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.435ns (routing 0.421ns, distribution 1.014ns)
  Clock Net Delay (Destination): 1.621ns (routing 0.472ns, distribution 1.149ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.435     1.555    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.594 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         0.106     1.700    d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X118Y1         FDCE                                         f  d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.621     1.768    d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X118Y1         FDCE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.039ns (26.865%)  route 0.106ns (73.135%))
  Logic Levels:           0  
  Clock Path Skew:        0.214ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.768ns
    Source Clock Delay      (SCD):    1.555ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.435ns (routing 0.421ns, distribution 1.014ns)
  Clock Net Delay (Destination): 1.621ns (routing 0.472ns, distribution 1.149ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.435     1.555    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.594 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         0.106     1.700    d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X118Y1         FDCE                                         f  d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.621     1.768    d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X118Y1         FDCE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.039ns (26.865%)  route 0.106ns (73.135%))
  Logic Levels:           0  
  Clock Path Skew:        0.214ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.768ns
    Source Clock Delay      (SCD):    1.555ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.435ns (routing 0.421ns, distribution 1.014ns)
  Clock Net Delay (Destination): 1.621ns (routing 0.472ns, distribution 1.149ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.435     1.555    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X117Y1         FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X117Y1         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.594 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=135, routed)         0.106     1.700    d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X118Y1         FDCE                                         f  d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.621     1.768    d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X118Y1         FDCE                                         r  d_1_i/axi_smc/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay            94 Endpoints
Min Delay           102 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.420ns  (logic 0.076ns (5.352%)  route 1.344ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.483ns, distribution 1.120ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.344     5.113    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.004    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.420ns  (logic 0.076ns (5.352%)  route 1.344ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.483ns, distribution 1.120ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.344     5.113    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.004    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[14]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.420ns  (logic 0.076ns (5.352%)  route 1.344ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.483ns, distribution 1.120ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.344     5.113    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[14]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.004    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[14]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.420ns  (logic 0.076ns (5.352%)  route 1.344ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.483ns, distribution 1.120ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.344     5.113    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.004    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.420ns  (logic 0.076ns (5.352%)  route 1.344ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.483ns, distribution 1.120ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.344     5.113    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.004    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.420ns  (logic 0.076ns (5.352%)  route 1.344ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.483ns, distribution 1.120ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.344     5.113    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.004    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.420ns  (logic 0.076ns (5.352%)  route 1.344ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.483ns, distribution 1.120ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.344     5.113    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.004    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.420ns  (logic 0.076ns (5.352%)  route 1.344ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.004ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.483ns, distribution 1.120ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.344     5.113    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.603     3.004    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.417ns  (logic 0.076ns (5.364%)  route 1.341ns (94.636%))
  Logic Levels:           0  
  Clock Path Skew:        -0.690ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.003ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.602ns (routing 0.483ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.341     5.110    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.602     3.003    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[17]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.417ns  (logic 0.076ns (5.364%)  route 1.341ns (94.636%))
  Logic Levels:           0  
  Clock Path Skew:        -0.690ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.003ns
    Source Clock Delay      (SCD):    3.693ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.506ns (routing 0.635ns, distribution 0.871ns)
  Clock Net Delay (Destination): 1.602ns (routing 0.483ns, distribution 1.119ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.236     2.159    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.187 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.506     3.693    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X99Y350        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y350        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.769 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         1.341     5.110    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[17]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.602     3.003    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[17]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.796%)  route 0.059ns (60.204%))
  Logic Levels:           0  
  Clock Path Skew:        4.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.376ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.835ns (routing 0.349ns, distribution 0.486ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.835     2.376    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362        FDCE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.415 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.059     2.474    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        4.035ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.399ns
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.823ns (routing 0.349ns, distribution 0.474ns)
  Clock Net Delay (Destination): 1.139ns (routing 0.330ns, distribution 0.809ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.823     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X96Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y371        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.403 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.085     2.488    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[0]
    SLICE_X96Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.139     6.399    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X96Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        4.029ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.394ns
    Source Clock Delay      (SCD):    2.365ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.824ns (routing 0.349ns, distribution 0.475ns)
  Clock Net Delay (Destination): 1.134ns (routing 0.330ns, distribution 0.804ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.824     2.365    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X93Y370        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y370        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.404 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.085     2.489    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[2]
    SLICE_X93Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.134     6.394    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X93Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        4.027ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.394ns
    Source Clock Delay      (SCD):    2.367ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.826ns (routing 0.349ns, distribution 0.477ns)
  Clock Net Delay (Destination): 1.134ns (routing 0.330ns, distribution 0.804ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.826     2.367    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X96Y373        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y373        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.406 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/Q
                         net (fo=1, routed)           0.085     2.491    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[3]
    SLICE_X96Y374        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.134     6.394    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X96Y374        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        4.030ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.403ns
    Source Clock Delay      (SCD):    2.373ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.832ns (routing 0.349ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.143ns (routing 0.330ns, distribution 0.813ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.832     2.373    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X101Y335       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y335       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.413 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.079     2.492    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[0]
    SLICE_X101Y336       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.143     6.403    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X101Y336       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        4.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.418ns
    Source Clock Delay      (SCD):    2.378ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.837ns (routing 0.349ns, distribution 0.488ns)
  Clock Net Delay (Destination): 1.158ns (routing 0.330ns, distribution 0.828ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.837     2.378    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X99Y335        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y335        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.417 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.085     2.502    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[2]
    SLICE_X99Y336        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.158     6.418    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X99Y336        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.040ns (28.169%)  route 0.102ns (71.831%))
  Logic Levels:           0  
  Clock Path Skew:        4.035ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.410ns
    Source Clock Delay      (SCD):    2.375ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.834ns (routing 0.349ns, distribution 0.485ns)
  Clock Net Delay (Destination): 1.150ns (routing 0.330ns, distribution 0.820ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.834     2.375    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X100Y335       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y335       FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.415 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.102     2.517    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[1]
    SLICE_X100Y336       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.150     6.410    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X100Y336       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.038ns (29.231%)  route 0.092ns (70.769%))
  Logic Levels:           0  
  Clock Path Skew:        3.995ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.383ns
    Source Clock Delay      (SCD):    2.388ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.847ns (routing 0.349ns, distribution 0.498ns)
  Clock Net Delay (Destination): 1.123ns (routing 0.330ns, distribution 0.793ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.847     2.388    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X82Y367        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y367        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.426 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.092     2.518    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X82Y367        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.123     6.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X82Y367        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.149ns  (logic 0.039ns (26.175%)  route 0.110ns (73.826%))
  Logic Levels:           0  
  Clock Path Skew:        4.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.396ns
    Source Clock Delay      (SCD):    2.376ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.835ns (routing 0.349ns, distribution 0.486ns)
  Clock Net Delay (Destination): 1.136ns (routing 0.330ns, distribution 0.806ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.835     2.376    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.415 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.110     2.525    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.136     6.396    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.039ns (24.684%)  route 0.119ns (75.317%))
  Logic Levels:           0  
  Clock Path Skew:        4.027ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.395ns
    Source Clock Delay      (SCD):    2.368ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.827ns (routing 0.349ns, distribution 0.478ns)
  Clock Net Delay (Destination): 1.135ns (routing 0.330ns, distribution 0.805ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.827     2.368    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X94Y370        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y370        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.407 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.119     2.526    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg[1]
    SLICE_X94Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.135     6.395    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X94Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_1_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.428ns  (logic 0.079ns (18.443%)  route 0.349ns (81.557%))
  Logic Levels:           0  
  Clock Path Skew:        1.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.461ns
    Source Clock Delay      (SCD):    3.318ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.645ns (routing 1.446ns, distribution 1.199ns)
  Clock Net Delay (Destination): 1.827ns (routing 0.632ns, distribution 1.195ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.207     0.543    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.673 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       2.645     3.318    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X58Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y220        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.397 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           0.349     3.746    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X58Y215        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.827     4.461    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X58Y215        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC1_CLK  {rise@0.000ns fall@1.220ns period=2.441ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.201ns  (logic 0.039ns (19.448%)  route 0.162ns (80.552%))
  Logic Levels:           0  
  Clock Path Skew:        0.767ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.559ns
    Source Clock Delay      (SCD):    1.792ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.443ns (routing 0.779ns, distribution 0.664ns)
  Clock Net Delay (Destination): 1.276ns (routing 0.432ns, distribution 0.844ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
    HSDAC_X0Y1           HSDAC (Prop_HSDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/CLK_DAC
                         net (fo=2, routed)           0.092     0.276    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt_0
    BUFG_GT_X1Y130       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.349 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac1_bufg_gt/O
    X2Y4 (CLOCK_ROOT)    net (fo=24383, routed)       1.443     1.792    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X58Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y220        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.831 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[9]/Q
                         net (fo=2, routed)           0.162     1.992    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X58Y215        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.276     2.559    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X58Y215        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_adc0_x2_0
  To Clock:  mmcm_clkout0

Max Delay           518 Endpoints
Min Delay           518 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_364_377/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[377]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.972ns  (logic 0.295ns (30.350%)  route 0.677ns (69.650%))
  Logic Levels:           0  
  Clock Path Skew:        -2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.405ns
    Source Clock Delay      (SCD):    6.703ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.201ns (routing 1.562ns, distribution 1.639ns)
  Clock Net Delay (Destination): 1.771ns (routing 0.632ns, distribution 1.139ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.201     6.703    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_364_377/WCLK
    SLICE_X99Y131        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_364_377/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y131        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     6.998 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_364_377/RAMG_D1/O
                         net (fo=1, routed)           0.677     7.675    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[377]
    SLICE_X104Y131       FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[377]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.771     4.405    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X104Y131       FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[377]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_378_391/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[386]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.951ns  (logic 0.288ns (30.284%)  route 0.663ns (69.716%))
  Logic Levels:           0  
  Clock Path Skew:        -2.284ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.405ns
    Source Clock Delay      (SCD):    6.689ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.187ns (routing 1.562ns, distribution 1.625ns)
  Clock Net Delay (Destination): 1.771ns (routing 0.632ns, distribution 1.139ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.187     6.689    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_378_391/WCLK
    SLICE_X97Y131        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_378_391/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y131        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     6.977 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_378_391/RAME/O
                         net (fo=1, routed)           0.663     7.640    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[386]
    SLICE_X104Y131       FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[386]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.771     4.405    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X104Y131       FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[386]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_322_335/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[322]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.884ns  (logic 0.289ns (32.692%)  route 0.595ns (67.308%))
  Logic Levels:           0  
  Clock Path Skew:        -2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.412ns
    Source Clock Delay      (SCD):    6.707ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.205ns (routing 1.562ns, distribution 1.643ns)
  Clock Net Delay (Destination): 1.778ns (routing 0.632ns, distribution 1.146ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.205     6.707    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_322_335/WCLK
    SLICE_X97Y111        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_322_335/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X97Y111        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     6.996 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_322_335/RAMA/O
                         net (fo=1, routed)           0.595     7.591    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[322]
    SLICE_X99Y109        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[322]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.778     4.412    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X99Y109        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[322]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_490_503/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[495]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.921ns  (logic 0.307ns (33.333%)  route 0.614ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        -2.301ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.328ns
    Source Clock Delay      (SCD):    6.629ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.127ns (routing 1.562ns, distribution 1.565ns)
  Clock Net Delay (Destination): 1.694ns (routing 0.632ns, distribution 1.062ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.127     6.629    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_490_503/WCLK
    SLICE_X83Y133        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_490_503/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y133        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     6.936 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_490_503/RAMC_D1/O
                         net (fo=1, routed)           0.614     7.550    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[495]
    SLICE_X89Y132        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[495]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.694     4.328    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X89Y132        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[495]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.897ns  (logic 0.295ns (32.887%)  route 0.602ns (67.113%))
  Logic Levels:           0  
  Clock Path Skew:        -2.308ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.337ns
    Source Clock Delay      (SCD):    6.645ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.143ns (routing 1.562ns, distribution 1.581ns)
  Clock Net Delay (Destination): 1.703ns (routing 0.632ns, distribution 1.071ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.143     6.645    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X90Y118        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y118        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     6.940 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/O
                         net (fo=1, routed)           0.602     7.542    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[38]
    SLICE_X93Y120        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.703     4.337    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X93Y120        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[38]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_364_377/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[371]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.825ns  (logic 0.301ns (36.485%)  route 0.524ns (63.515%))
  Logic Levels:           0  
  Clock Path Skew:        -2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.405ns
    Source Clock Delay      (SCD):    6.703ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.201ns (routing 1.562ns, distribution 1.639ns)
  Clock Net Delay (Destination): 1.771ns (routing 0.632ns, distribution 1.139ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.201     6.703    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_364_377/WCLK
    SLICE_X99Y131        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_364_377/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y131        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     7.004 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_364_377/RAMD_D1/O
                         net (fo=1, routed)           0.524     7.528    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[371]
    SLICE_X104Y131       FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[371]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.771     4.405    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X104Y131       FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[371]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_504_511/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[507]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.909ns  (logic 0.307ns (33.773%)  route 0.602ns (66.227%))
  Logic Levels:           0  
  Clock Path Skew:        -2.293ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.326ns
    Source Clock Delay      (SCD):    6.618ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.116ns (routing 1.562ns, distribution 1.554ns)
  Clock Net Delay (Destination): 1.692ns (routing 0.632ns, distribution 1.060ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.116     6.618    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_504_511/WCLK
    SLICE_X83Y130        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_504_511/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y130        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.307     6.925 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_504_511/RAMB_D1/O
                         net (fo=1, routed)           0.602     7.527    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[507]
    SLICE_X86Y129        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[507]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.692     4.326    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X86Y129        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[507]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_265/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[265]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.879ns  (logic 0.295ns (33.561%)  route 0.584ns (66.439%))
  Logic Levels:           0  
  Clock Path Skew:        -2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.338ns
    Source Clock Delay      (SCD):    6.637ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.135ns (routing 1.562ns, distribution 1.573ns)
  Clock Net Delay (Destination): 1.704ns (routing 0.632ns, distribution 1.072ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.135     6.637    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_265/WCLK
    SLICE_X89Y104        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_265/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y104        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     6.932 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_265/RAMG_D1/O
                         net (fo=1, routed)           0.584     7.516    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[265]
    SLICE_X91Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[265]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.704     4.338    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X91Y103        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[265]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.884ns  (logic 0.292ns (33.032%)  route 0.592ns (66.968%))
  Logic Levels:           0  
  Clock Path Skew:        -2.292ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.333ns
    Source Clock Delay      (SCD):    6.625ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.123ns (routing 1.562ns, distribution 1.561ns)
  Clock Net Delay (Destination): 1.699ns (routing 0.632ns, distribution 1.067ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.123     6.625    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X89Y125        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y125        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     6.917 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMB/O
                         net (fo=1, routed)           0.592     7.509    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[2]
    SLICE_X92Y121        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.699     4.333    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X92Y121        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[32]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.864ns  (logic 0.288ns (33.333%)  route 0.576ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        -2.294ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.351ns
    Source Clock Delay      (SCD):    6.645ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      3.143ns (routing 1.562ns, distribution 1.581ns)
  Clock Net Delay (Destination): 1.717ns (routing 0.632ns, distribution 1.085ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.247     0.397    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.527 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.830     3.357    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.230 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.244     3.474    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.502 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       3.143     6.645    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X90Y118        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y118        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     6.933 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC/O
                         net (fo=1, routed)           0.576     7.509    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[32]
    SLICE_X93Y119        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[32]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.717     4.351    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X93Y119        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[32]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[195]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.165ns  (logic 0.105ns (63.636%)  route 0.060ns (36.364%))
  Logic Levels:           0  
  Clock Path Skew:        -1.314ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.548ns
    Source Clock Delay      (SCD):    3.862ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.656ns (routing 0.858ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.432ns, distribution 0.833ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.656     3.862    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/WCLK
    SLICE_X78Y127        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y127        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.967 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMG_D1/O
                         net (fo=1, routed)           0.060     4.027    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[195]
    SLICE_X77Y127        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[195]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.265     2.548    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X77Y127        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[195]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[221]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.169ns  (logic 0.111ns (65.681%)  route 0.058ns (34.320%))
  Logic Levels:           0  
  Clock Path Skew:        -1.321ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.539ns
    Source Clock Delay      (SCD):    3.860ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.654ns (routing 0.858ns, distribution 0.796ns)
  Clock Net Delay (Destination): 1.256ns (routing 0.432ns, distribution 0.824ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.654     3.860    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/WCLK
    SLICE_X78Y132        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y132        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.971 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMF_D1/O
                         net (fo=1, routed)           0.058     4.029    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[221]
    SLICE_X77Y132        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[221]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.256     2.539    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X77Y132        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[221]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[223]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.105ns (61.765%)  route 0.065ns (38.235%))
  Logic Levels:           0  
  Clock Path Skew:        -1.325ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.535ns
    Source Clock Delay      (SCD):    3.860ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.654ns (routing 0.858ns, distribution 0.796ns)
  Clock Net Delay (Destination): 1.252ns (routing 0.432ns, distribution 0.820ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.654     3.860    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/WCLK
    SLICE_X78Y132        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y132        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.965 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMG_D1/O
                         net (fo=1, routed)           0.065     4.030    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[223]
    SLICE_X78Y131        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[223]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.252     2.535    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X78Y131        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[223]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[101]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.169ns  (logic 0.110ns (65.089%)  route 0.059ns (34.911%))
  Logic Levels:           0  
  Clock Path Skew:        -1.321ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.541ns
    Source Clock Delay      (SCD):    3.862ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.656ns (routing 0.858ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.258ns (routing 0.432ns, distribution 0.826ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.656     3.862    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X78Y122        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y122        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.110     3.972 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMB_D1/O
                         net (fo=1, routed)           0.059     4.031    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[101]
    SLICE_X77Y122        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[101]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.258     2.541    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X77Y122        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[101]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[165]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.174ns  (logic 0.111ns (63.793%)  route 0.063ns (36.207%))
  Logic Levels:           0  
  Clock Path Skew:        -1.325ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.536ns
    Source Clock Delay      (SCD):    3.861ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.655ns (routing 0.858ns, distribution 0.797ns)
  Clock Net Delay (Destination): 1.253ns (routing 0.432ns, distribution 0.821ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.655     3.861    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167/WCLK
    SLICE_X78Y130        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y130        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.972 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_154_167/RAMF_D1/O
                         net (fo=1, routed)           0.063     4.035    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[165]
    SLICE_X78Y129        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[165]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.253     2.536    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X78Y129        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[165]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[111]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.174ns  (logic 0.105ns (60.345%)  route 0.069ns (39.655%))
  Logic Levels:           0  
  Clock Path Skew:        -1.317ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.545ns
    Source Clock Delay      (SCD):    3.862ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.656ns (routing 0.858ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.262ns (routing 0.432ns, distribution 0.830ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.656     3.862    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X78Y122        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y122        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.967 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMG_D1/O
                         net (fo=1, routed)           0.069     4.036    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[111]
    SLICE_X77Y122        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[111]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.262     2.545    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X77Y122        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[111]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[185]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.175ns  (logic 0.110ns (62.857%)  route 0.065ns (37.143%))
  Logic Levels:           0  
  Clock Path Skew:        -1.313ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.549ns
    Source Clock Delay      (SCD):    3.862ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.656ns (routing 0.858ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.432ns, distribution 0.834ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.656     3.862    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/WCLK
    SLICE_X78Y127        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y127        RAMD32 (Prop_B6LUT_SLICEM_CLK_O)
                                                      0.110     3.972 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMB_D1/O
                         net (fo=1, routed)           0.065     4.037    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[185]
    SLICE_X76Y127        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[185]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.266     2.549    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X76Y127        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[185]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[139]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.165ns  (logic 0.105ns (63.636%)  route 0.060ns (36.364%))
  Logic Levels:           0  
  Clock Path Skew:        -1.322ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.553ns
    Source Clock Delay      (SCD):    3.875ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.669ns (routing 0.858ns, distribution 0.811ns)
  Clock Net Delay (Destination): 1.270ns (routing 0.432ns, distribution 0.838ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.669     3.875    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X79Y119        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y119        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     3.980 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMG_D1/O
                         net (fo=1, routed)           0.060     4.040    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[139]
    SLICE_X80Y119        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[139]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.270     2.553    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X80Y119        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[139]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[176]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.108ns (60.000%)  route 0.072ns (40.000%))
  Logic Levels:           0  
  Clock Path Skew:        -1.330ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.534ns
    Source Clock Delay      (SCD):    3.864ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.658ns (routing 0.858ns, distribution 0.800ns)
  Clock Net Delay (Destination): 1.251ns (routing 0.432ns, distribution 0.819ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.658     3.864    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/WCLK
    SLICE_X79Y125        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y125        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     3.972 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_168_181/RAME/O
                         net (fo=1, routed)           0.072     4.044    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[176]
    SLICE_X80Y125        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[176]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.251     2.534    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X80Y125        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[176]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Destination:            d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[137]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.111ns (65.294%)  route 0.059ns (34.706%))
  Logic Levels:           0  
  Clock Path Skew:        -1.322ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.553ns
    Source Clock Delay      (SCD):    3.875ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.220ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.176ns
    Phase Error              (PE):    0.125ns
  Clock Net Delay (Source):      1.669ns (routing 0.858ns, distribution 0.811ns)
  Clock Net Delay (Destination): 1.270ns (routing 0.432ns, distribution 0.838ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.111     0.190    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.263 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.551     1.814    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     2.044 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.145     2.189    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.206 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.669     3.875    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X79Y119        RAMD32                                       r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y119        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     3.986 r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMF_D1/O
                         net (fo=1, routed)           0.059     4.045    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg0[137]
    SLICE_X80Y119        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[137]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.270     2.553    d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X80Y119        FDRE                                         r  d_1_i/ddr4/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_rd_b_synth_template.gen_rf_narrow_pipe.doutb_reg_reg[137]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  mmcm_clkout0

Max Delay           106 Endpoints
Min Delay           106 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.171ns  (logic 0.079ns (6.747%)  route 1.092ns (93.253%))
  Logic Levels:           0  
  Clock Path Skew:        2.146ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.542ns
    Source Clock Delay      (SCD):    2.396ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.170ns (routing 0.777ns, distribution 1.393ns)
  Clock Net Delay (Destination): 1.908ns (routing 0.632ns, distribution 1.276ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.170     2.396    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y148        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.475 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[4]/Q
                         net (fo=2, routed)           1.092     3.567    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[4]
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.908     4.542    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.104ns  (logic 0.079ns (7.155%)  route 1.025ns (92.845%))
  Logic Levels:           0  
  Clock Path Skew:        2.146ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.542ns
    Source Clock Delay      (SCD):    2.396ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.170ns (routing 0.777ns, distribution 1.393ns)
  Clock Net Delay (Destination): 1.908ns (routing 0.632ns, distribution 1.276ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.170     2.396    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y148        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.475 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[6]/Q
                         net (fo=2, routed)           1.025     3.500    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[6]
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.908     4.542    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.055ns  (logic 0.078ns (7.393%)  route 0.977ns (92.607%))
  Logic Levels:           0  
  Clock Path Skew:        2.146ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.545ns
    Source Clock Delay      (SCD):    2.399ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.173ns (routing 0.777ns, distribution 1.396ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.632ns, distribution 1.279ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.173     2.399    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X39Y150        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y150        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.477 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[6]/Q
                         net (fo=2, routed)           0.977     3.454    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[6]
    SLICE_X39Y150        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.911     4.545    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X39Y150        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.053ns  (logic 0.079ns (7.502%)  route 0.974ns (92.498%))
  Logic Levels:           0  
  Clock Path Skew:        2.146ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.542ns
    Source Clock Delay      (SCD):    2.396ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.170ns (routing 0.777ns, distribution 1.393ns)
  Clock Net Delay (Destination): 1.908ns (routing 0.632ns, distribution 1.276ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.170     2.396    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y148        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.475 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[0]/Q
                         net (fo=2, routed)           0.974     3.449    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[0]
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.908     4.542    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.024ns  (logic 0.076ns (7.422%)  route 0.948ns (92.578%))
  Logic Levels:           0  
  Clock Path Skew:        2.145ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.565ns
    Source Clock Delay      (SCD):    2.420ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.194ns (routing 0.777ns, distribution 1.417ns)
  Clock Net Delay (Destination): 1.931ns (routing 0.632ns, distribution 1.299ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.194     2.420    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X46Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y164        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     2.496 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[26]/Q
                         net (fo=2, routed)           0.948     3.444    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[26]
    SLICE_X39Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.931     4.565    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X39Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[26]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.010ns  (logic 0.079ns (7.822%)  route 0.931ns (92.179%))
  Logic Levels:           0  
  Clock Path Skew:        2.145ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.565ns
    Source Clock Delay      (SCD):    2.420ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.194ns (routing 0.777ns, distribution 1.417ns)
  Clock Net Delay (Destination): 1.931ns (routing 0.632ns, distribution 1.299ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.194     2.420    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X46Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y164        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.499 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[25]/Q
                         net (fo=2, routed)           0.931     3.430    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[25]
    SLICE_X39Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.931     4.565    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X39Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[25]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg0_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/start_reg_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.977ns  (logic 0.079ns (8.086%)  route 0.898ns (91.914%))
  Logic Levels:           0  
  Clock Path Skew:        2.116ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.531ns
    Source Clock Delay      (SCD):    2.415ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.189ns (routing 0.777ns, distribution 1.412ns)
  Clock Net Delay (Destination): 1.897ns (routing 0.632ns, distribution 1.265ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.189     2.415    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X43Y149        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg0_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y149        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.494 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg0_reg[0]/Q
                         net (fo=2, routed)           0.898     3.392    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/start_reg_resync_i/RSTART_REG
    SLICE_X43Y149        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/start_reg_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.897     4.531    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/start_reg_resync_i/aclk
    SLICE_X43Y149        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/start_reg_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.932ns  (logic 0.078ns (8.372%)  route 0.854ns (91.628%))
  Logic Levels:           0  
  Clock Path Skew:        2.111ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.509ns
    Source Clock Delay      (SCD):    2.398ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.172ns (routing 0.777ns, distribution 1.395ns)
  Clock Net Delay (Destination): 1.875ns (routing 0.632ns, distribution 1.243ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.172     2.398    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X42Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y148        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.476 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[7]/Q
                         net (fo=2, routed)           0.854     3.330    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[7]
    SLICE_X52Y161        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.875     4.509    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X52Y161        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.933ns  (logic 0.081ns (8.681%)  route 0.852ns (91.319%))
  Logic Levels:           0  
  Clock Path Skew:        2.146ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.542ns
    Source Clock Delay      (SCD):    2.396ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.170ns (routing 0.777ns, distribution 1.393ns)
  Clock Net Delay (Destination): 1.908ns (routing 0.632ns, distribution 1.276ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.170     2.396    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y148        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.477 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/Q
                         net (fo=2, routed)           0.852     3.329    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[7]
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.908     4.542    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.902ns  (logic 0.079ns (8.754%)  route 0.823ns (91.246%))
  Logic Levels:           0  
  Clock Path Skew:        2.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.538ns
    Source Clock Delay      (SCD):    2.387ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.161ns (routing 0.777ns, distribution 1.384ns)
  Clock Net Delay (Destination): 1.904ns (routing 0.632ns, distribution 1.272ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.161     2.387    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y142        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y142        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     2.466 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[12]/Q
                         net (fo=2, routed)           0.823     3.290    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[12]
    SLICE_X42Y156        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.904     4.538    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X42Y156        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[12]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.040ns (31.173%)  route 0.088ns (68.827%))
  Logic Levels:           0  
  Clock Path Skew:        1.305ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.604ns
    Source Clock Delay      (SCD):    1.299ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.179ns (routing 0.421ns, distribution 0.758ns)
  Clock Net Delay (Destination): 1.321ns (routing 0.432ns, distribution 0.889ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.179     1.299    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y154        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y154        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.339 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[21]/Q
                         net (fo=2, routed)           0.088     1.427    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[21]
    SLICE_X49Y154        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.321     2.604    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y154        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[21]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.246%)  route 0.080ns (66.754%))
  Logic Levels:           0  
  Clock Path Skew:        1.299ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.607ns
    Source Clock Delay      (SCD):    1.308ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.188ns (routing 0.421ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.324ns (routing 0.432ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.188     1.308    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y164        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.348 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[25]/Q
                         net (fo=2, routed)           0.080     1.428    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[25]
    SLICE_X49Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.324     2.607    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[25]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.038ns (29.356%)  route 0.091ns (70.644%))
  Logic Levels:           0  
  Clock Path Skew:        1.304ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.605ns
    Source Clock Delay      (SCD):    1.301ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.181ns (routing 0.421ns, distribution 0.760ns)
  Clock Net Delay (Destination): 1.322ns (routing 0.432ns, distribution 0.890ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.181     1.301    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X48Y154        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y154        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.339 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[24]/Q
                         net (fo=2, routed)           0.091     1.430    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[24]
    SLICE_X48Y154        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.322     2.605    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X48Y154        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[24]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (32.927%)  route 0.079ns (67.073%))
  Logic Levels:           0  
  Clock Path Skew:        1.295ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.607ns
    Source Clock Delay      (SCD):    1.312ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.192ns (routing 0.421ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.324ns (routing 0.432ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.192     1.312    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X43Y150        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y150        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.351 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[0]/Q
                         net (fo=2, routed)           0.079     1.430    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[0]
    SLICE_X43Y150        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.324     2.607    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X43Y150        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.123ns  (logic 0.040ns (32.437%)  route 0.083ns (67.563%))
  Logic Levels:           0  
  Clock Path Skew:        1.310ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.619ns
    Source Clock Delay      (SCD):    1.309ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.189ns (routing 0.421ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.336ns (routing 0.432ns, distribution 0.904ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.189     1.309    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y148        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.349 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[5]/Q
                         net (fo=2, routed)           0.083     1.432    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[5]
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.336     2.619    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.040ns (31.667%)  route 0.086ns (68.333%))
  Logic Levels:           0  
  Clock Path Skew:        1.293ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.602ns
    Source Clock Delay      (SCD):    1.309ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.189ns (routing 0.421ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.432ns, distribution 0.887ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.189     1.309    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[17]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y157        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.349 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[17]/Q
                         net (fo=2, routed)           0.086     1.435    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[17]
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.319     2.602    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[17]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.126ns  (logic 0.039ns (30.875%)  route 0.087ns (69.125%))
  Logic Levels:           0  
  Clock Path Skew:        1.293ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.602ns
    Source Clock Delay      (SCD):    1.309ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.189ns (routing 0.421ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.432ns, distribution 0.887ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.189     1.309    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y157        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.348 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[22]/Q
                         net (fo=2, routed)           0.087     1.435    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[22]
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.319     2.602    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[22]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.040ns (31.328%)  route 0.088ns (68.672%))
  Logic Levels:           0  
  Clock Path Skew:        1.310ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.619ns
    Source Clock Delay      (SCD):    1.309ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.189ns (routing 0.421ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.336ns (routing 0.432ns, distribution 0.904ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.189     1.309    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y148        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.349 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[3]/Q
                         net (fo=2, routed)           0.088     1.437    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[3]
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.336     2.619    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X38Y148        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.364%)  route 0.089ns (69.636%))
  Logic Levels:           0  
  Clock Path Skew:        1.293ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.602ns
    Source Clock Delay      (SCD):    1.309ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.189ns (routing 0.421ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.432ns, distribution 0.887ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.189     1.309    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X47Y157        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.348 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/Q
                         net (fo=2, routed)           0.089     1.437    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[20]
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.319     2.602    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X47Y157        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[30]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.039ns (30.073%)  route 0.091ns (69.927%))
  Logic Levels:           0  
  Clock Path Skew:        1.299ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.607ns
    Source Clock Delay      (SCD):    1.308ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.188ns (routing 0.421ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.324ns (routing 0.432ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.188     1.308    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[30]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y164        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.347 r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[30]/Q
                         net (fo=2, routed)           0.091     1.438    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[30]
    SLICE_X49Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.324     2.607    d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X49Y164        FDRE                                         r  d_1_i/ddr4/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[30]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Max Delay            68 Endpoints
Min Delay            68 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.339ns  (logic 0.078ns (3.334%)  route 2.261ns (96.666%))
  Logic Levels:           0  
  Clock Path Skew:        0.516ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.742ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 2.108ns (routing 0.632ns, distribution 1.476ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.261     6.565    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X11Y193        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.108     4.742    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X11Y193        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.339ns  (logic 0.078ns (3.334%)  route 2.261ns (96.666%))
  Logic Levels:           0  
  Clock Path Skew:        0.516ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.742ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 2.108ns (routing 0.632ns, distribution 1.476ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.261     6.565    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X11Y193        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.108     4.742    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X11Y193        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.339ns  (logic 0.078ns (3.334%)  route 2.261ns (96.666%))
  Logic Levels:           0  
  Clock Path Skew:        0.516ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.742ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 2.108ns (routing 0.632ns, distribution 1.476ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.261     6.565    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X11Y193        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.108     4.742    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X11Y193        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_transaction_regulator/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.029ns  (logic 0.078ns (3.844%)  route 1.951ns (96.156%))
  Logic Levels:           0  
  Clock Path Skew:        0.279ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.505ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 1.871ns (routing 0.632ns, distribution 1.239ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.951     6.255    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X51Y230        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.871     4.505    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X51Y230        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.029ns  (logic 0.078ns (3.844%)  route 1.951ns (96.156%))
  Logic Levels:           0  
  Clock Path Skew:        0.279ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.505ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 1.871ns (routing 0.632ns, distribution 1.239ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.951     6.255    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X51Y230        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.871     4.505    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X51Y230        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.029ns  (logic 0.078ns (3.844%)  route 1.951ns (96.156%))
  Logic Levels:           0  
  Clock Path Skew:        0.279ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.505ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 1.871ns (routing 0.632ns, distribution 1.239ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.951     6.255    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X51Y230        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.871     4.505    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X51Y230        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.026ns  (logic 0.078ns (3.849%)  route 1.948ns (96.151%))
  Logic Levels:           0  
  Clock Path Skew:        0.500ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.726ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 2.092ns (routing 0.632ns, distribution 1.460ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.948     6.252    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X13Y187        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.092     4.726    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X13Y187        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.026ns  (logic 0.078ns (3.849%)  route 1.948ns (96.151%))
  Logic Levels:           0  
  Clock Path Skew:        0.500ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.726ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 2.092ns (routing 0.632ns, distribution 1.460ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.948     6.252    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X13Y187        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.092     4.726    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X13Y187        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.026ns  (logic 0.078ns (3.849%)  route 1.948ns (96.151%))
  Logic Levels:           0  
  Clock Path Skew:        0.500ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.726ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 2.092ns (routing 0.632ns, distribution 1.460ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.948     6.252    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/src_arst
    SLICE_X13Y187        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.092     4.726    d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/dest_clk
    SLICE_X13Y187        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.008ns  (logic 0.078ns (3.884%)  route 1.930ns (96.116%))
  Logic Levels:           0  
  Clock Path Skew:        0.193ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.419ns
    Source Clock Delay      (SCD):    4.226ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.030ns (routing 0.696ns, distribution 1.334ns)
  Clock Net Delay (Destination): 1.785ns (routing 0.632ns, distribution 1.153ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       2.030     4.226    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     4.304 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          1.930     6.234    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X108Y161       FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.785     4.419    d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X108Y161       FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.252ns  (logic 0.039ns (15.504%)  route 0.213ns (84.496%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.548ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.116ns (routing 0.385ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.432ns, distribution 0.834ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.116     2.663    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.702 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.213     2.915    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X64Y182        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.266     2.548    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X64Y182        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.252ns  (logic 0.039ns (15.504%)  route 0.213ns (84.496%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.548ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.116ns (routing 0.385ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.432ns, distribution 0.834ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.116     2.663    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.702 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.213     2.915    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X64Y182        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.266     2.548    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X64Y182        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.252ns  (logic 0.039ns (15.504%)  route 0.213ns (84.496%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.548ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.116ns (routing 0.385ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.266ns (routing 0.432ns, distribution 0.834ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.116     2.663    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.702 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.213     2.915    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X64Y182        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.266     2.548    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X64Y182        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.331ns  (logic 0.039ns (11.782%)  route 0.292ns (88.218%))
  Logic Levels:           0  
  Clock Path Skew:        -0.049ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.569ns
    Source Clock Delay      (SCD):    2.618ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.071ns (routing 0.385ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.286ns (routing 0.432ns, distribution 0.854ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.071     2.618    d_1_i/ddr4/ddr4_0/inst/c0_ddr4_ui_clk
    SLICE_X81Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y318        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.657 r  d_1_i/ddr4/ddr4_0/inst/div_clk_rst_r1_reg/Q
                         net (fo=1, routed)           0.292     2.949    d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X76Y318        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.286     2.569    d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X76Y318        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.310ns  (logic 0.053ns (17.076%)  route 0.257ns (82.924%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.540ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.095ns (routing 0.385ns, distribution 0.710ns)
  Clock Net Delay (Destination): 1.257ns (routing 0.432ns, distribution 0.825ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.095     2.642    d_1_i/ddr4/rst_ddr4/U0/slowest_sync_clk
    SLICE_X78Y181        FDRE                                         r  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X78Y181        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.680 f  d_1_i/ddr4/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=2, routed)           0.242     2.922    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aresetn
    SLICE_X65Y191        LUT1 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     2.937 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.015     2.952    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/asr_d1
    SLICE_X65Y191        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.257     2.540    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aclk
    SLICE_X65Y191        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.383ns  (logic 0.039ns (10.196%)  route 0.344ns (89.804%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.548ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.116ns (routing 0.385ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.432ns, distribution 0.833ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.116     2.663    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.702 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.344     3.046    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X61Y190        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.265     2.548    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X61Y190        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.383ns  (logic 0.039ns (10.196%)  route 0.344ns (89.804%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.548ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.116ns (routing 0.385ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.432ns, distribution 0.833ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.116     2.663    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.702 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.344     3.046    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X61Y190        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.265     2.548    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X61Y190        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.383ns  (logic 0.039ns (10.196%)  route 0.344ns (89.804%))
  Logic Levels:           0  
  Clock Path Skew:        -0.115ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.548ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.116ns (routing 0.385ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.432ns, distribution 0.833ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.116     2.663    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.702 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.344     3.046    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X61Y190        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.265     2.548    d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X61Y190        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/m00_nodes/m00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.386ns  (logic 0.039ns (10.109%)  route 0.347ns (89.891%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.570ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.116ns (routing 0.385ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.287ns (routing 0.432ns, distribution 0.855ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.116     2.663    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.702 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.347     3.049    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X59Y188        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.287     2.570    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X59Y188        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.386ns  (logic 0.039ns (10.109%)  route 0.347ns (89.891%))
  Logic Levels:           0  
  Clock Path Skew:        -0.093ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.570ns
    Source Clock Delay      (SCD):    2.663ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.116ns (routing 0.385ns, distribution 0.731ns)
  Clock Net Delay (Destination): 1.287ns (routing 0.432ns, distribution 0.855ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.116     2.663    d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X70Y181        FDRE                                         r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X70Y181        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.702 r  d_1_i/ddr4/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.347     3.049    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X59Y188        FDCE                                         f  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.287     2.570    d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X59Y188        FDCE                                         r  d_1_i/ddr4/axi_smc_1/inst/s00_nodes/s00_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay            28 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.109ns  (logic 0.039ns (35.749%)  route 0.070ns (64.251%))
  Logic Levels:           0  
  Clock Path Skew:        0.158ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.512ns
    Source Clock Delay      (SCD):    2.354ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.813ns (routing 0.349ns, distribution 0.464ns)
  Clock Net Delay (Destination): 1.230ns (routing 0.432ns, distribution 0.798ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.813     2.354    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X87Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y356        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.393 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_en_lvl_reg/Q
                         net (fo=2, routed)           0.070     2.463    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/D[0]
    SLICE_X87Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.230     2.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]_0
    SLICE_X87Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_en_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.039ns (37.143%)  route 0.066ns (62.857%))
  Logic Levels:           0  
  Clock Path Skew:        0.125ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.493ns
    Source Clock Delay      (SCD):    2.368ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.827ns (routing 0.349ns, distribution 0.478ns)
  Clock Net Delay (Destination): 1.210ns (routing 0.432ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.827     2.368    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X82Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y355        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     2.407 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/Q
                         net (fo=1, routed)           0.066     2.473    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[4]
    SLICE_X82Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.210     2.493    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X82Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.051%)  route 0.079ns (66.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.139ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.496ns
    Source Clock Delay      (SCD):    2.357ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.816ns (routing 0.349ns, distribution 0.467ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.432ns, distribution 0.781ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.816     2.357    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X85Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y358        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.396 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[6]/Q
                         net (fo=1, routed)           0.079     2.475    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[6]
    SLICE_X85Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.213     2.496    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X85Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.494ns
    Source Clock Delay      (SCD):    2.366ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.825ns (routing 0.349ns, distribution 0.476ns)
  Clock Net Delay (Destination): 1.211ns (routing 0.432ns, distribution 0.779ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.825     2.366    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X81Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y355        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.406 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/Q
                         net (fo=1, routed)           0.080     2.486    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[2]
    SLICE_X81Y353        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.211     2.494    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[7].sync_reg_reg[1]_0
    SLICE_X81Y353        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.040ns (29.851%)  route 0.094ns (70.149%))
  Logic Levels:           0  
  Clock Path Skew:        0.146ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.503ns
    Source Clock Delay      (SCD):    2.357ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.816ns (routing 0.349ns, distribution 0.467ns)
  Clock Net Delay (Destination): 1.220ns (routing 0.432ns, distribution 0.788ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.816     2.357    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X87Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y358        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     2.397 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/Q
                         net (fo=1, routed)           0.094     2.491    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[15]
    SLICE_X89Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.220     2.503    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X89Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.139ns  (logic 0.039ns (28.058%)  route 0.100ns (71.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.142ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.498ns
    Source Clock Delay      (SCD):    2.356ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.815ns (routing 0.349ns, distribution 0.466ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.432ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.815     2.356    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X86Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y359        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/Q
                         net (fo=1, routed)           0.100     2.495    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/D[0]
    SLICE_X86Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.215     2.498    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[1]_0
    SLICE_X86Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.153ns  (logic 0.037ns (24.183%)  route 0.116ns (75.817%))
  Logic Levels:           0  
  Clock Path Skew:        0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.502ns
    Source Clock Delay      (SCD):    2.357ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.816ns (routing 0.349ns, distribution 0.467ns)
  Clock Net Delay (Destination): 1.219ns (routing 0.432ns, distribution 0.787ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.816     2.357    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X87Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y358        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.394 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/Q
                         net (fo=1, routed)           0.116     2.510    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[11]
    SLICE_X86Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.219     2.502    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X86Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[9].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.155ns  (logic 0.037ns (23.871%)  route 0.118ns (76.129%))
  Logic Levels:           0  
  Clock Path Skew:        0.142ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.498ns
    Source Clock Delay      (SCD):    2.356ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.815ns (routing 0.349ns, distribution 0.466ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.432ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.815     2.356    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X86Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y358        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.393 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[9]/Q
                         net (fo=1, routed)           0.118     2.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[9]
    SLICE_X86Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[9].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.215     2.498    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X86Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[9].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.037ns (26.056%)  route 0.105ns (73.944%))
  Logic Levels:           0  
  Clock Path Skew:        0.124ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.493ns
    Source Clock Delay      (SCD):    2.369ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.828ns (routing 0.349ns, distribution 0.479ns)
  Clock Net Delay (Destination): 1.210ns (routing 0.432ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.828     2.369    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X83Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y359        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.406 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/Q
                         net (fo=1, routed)           0.105     2.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[3]
    SLICE_X83Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.210     2.493    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X83Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.164ns  (logic 0.038ns (23.171%)  route 0.126ns (76.829%))
  Logic Levels:           0  
  Clock Path Skew:        0.151ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.503ns
    Source Clock Delay      (SCD):    2.352ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.811ns (routing 0.349ns, distribution 0.462ns)
  Clock Net Delay (Destination): 1.220ns (routing 0.432ns, distribution 0.788ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.140     1.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.541 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.811     2.352    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X89Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y354        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.390 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/Q
                         net (fo=1, routed)           0.126     2.516    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[0]
    SLICE_X89Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.220     2.503    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[1]_0
    SLICE_X89Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay           129 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.115ns  (logic 0.038ns (33.135%)  route 0.077ns (66.865%))
  Logic Levels:           0  
  Clock Path Skew:        -0.142ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.452ns
    Source Clock Delay      (SCD):    2.594ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.037ns (routing 0.391ns, distribution 0.646ns)
  Clock Net Delay (Destination): 1.170ns (routing 0.432ns, distribution 0.738ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.037     2.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y217        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y217        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.632 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[2]/Q
                         net (fo=2, routed)           0.077     2.709    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/phy2clb_phy_rdy_upp_riuclk[2]
    SLICE_X83Y217        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.170     2.452    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X83Y217        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.038ns (31.148%)  route 0.084ns (68.852%))
  Logic Levels:           0  
  Clock Path Skew:        -0.125ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.485ns
    Source Clock Delay      (SCD):    2.610ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.053ns (routing 0.391ns, distribution 0.662ns)
  Clock Net Delay (Destination): 1.203ns (routing 0.432ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.053     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X87Y276        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y276        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.648 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[13]/Q
                         net (fo=1, routed)           0.084     2.732    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[13]
    SLICE_X87Y277        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.203     2.485    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X87Y277        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[13].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy_ready_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_ready_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.091ns  (logic 0.039ns (42.857%)  route 0.052ns (57.143%))
  Logic Levels:           0  
  Clock Path Skew:        -0.153ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.489ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.085ns (routing 0.391ns, distribution 0.694ns)
  Clock Net Delay (Destination): 1.206ns (routing 0.432ns, distribution 0.774ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.085     2.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy_ready_riuclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y303        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.681 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy_ready_riuclk_reg/Q
                         net (fo=1, routed)           0.052     2.733    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_ready_sync/D[0]
    SLICE_X81Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_ready_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.206     2.489    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_ready_sync/SYNC[0].sync_reg_reg[0]_0
    SLICE_X81Y303        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_ready_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.040ns (31.084%)  route 0.089ns (68.916%))
  Logic Levels:           0  
  Clock Path Skew:        -0.158ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.447ns
    Source Clock Delay      (SCD):    2.605ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.048ns (routing 0.391ns, distribution 0.657ns)
  Clock Net Delay (Destination): 1.164ns (routing 0.432ns, distribution 0.732ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.048     2.605    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y231        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y231        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.645 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_phy_rdy_upp_riuclk_int_reg[3]/Q
                         net (fo=2, routed)           0.089     2.733    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/phy2clb_phy_rdy_upp_riuclk[3]
    SLICE_X81Y232        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.164     2.447    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y232        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_phy_rdy_upp/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.038ns (28.857%)  route 0.094ns (71.143%))
  Logic Levels:           0  
  Clock Path Skew:        -0.152ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.450ns
    Source Clock Delay      (SCD):    2.602ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.045ns (routing 0.391ns, distribution 0.654ns)
  Clock Net Delay (Destination): 1.167ns (routing 0.432ns, distribution 0.735ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.045     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y181        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y181        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.640 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[0]/Q
                         net (fo=2, routed)           0.094     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/phy2clb_fixdly_rdy_low_riuclk[0]
    SLICE_X81Y182        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.167     2.450    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y182        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (32.051%)  route 0.083ns (67.950%))
  Logic Levels:           0  
  Clock Path Skew:        -0.146ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.468ns
    Source Clock Delay      (SCD):    2.614ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.057ns (routing 0.391ns, distribution 0.666ns)
  Clock Net Delay (Destination): 1.185ns (routing 0.432ns, distribution 0.753ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.057     2.614    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X84Y273        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y273        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.653 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[6]/Q
                         net (fo=2, routed)           0.083     2.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/phy2clb_fixdly_rdy_low_riuclk[6]
    SLICE_X84Y273        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.185     2.468    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[19].sync_reg_reg[1]_0
    SLICE_X84Y273        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.139ns  (logic 0.038ns (27.397%)  route 0.101ns (72.603%))
  Logic Levels:           0  
  Clock Path Skew:        -0.152ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.445ns
    Source Clock Delay      (SCD):    2.597ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.040ns (routing 0.391ns, distribution 0.649ns)
  Clock Net Delay (Destination): 1.162ns (routing 0.432ns, distribution 0.730ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.040     2.597    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X83Y195        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y195        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.635 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_upp_riuclk_int_reg[0]/Q
                         net (fo=2, routed)           0.101     2.736    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/phy2clb_fixdly_rdy_upp_riuclk[0]
    SLICE_X82Y196        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.162     2.445    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[19].sync_reg_reg[1]_0
    SLICE_X82Y196        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_upp/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.111ns  (logic 0.039ns (35.135%)  route 0.072ns (64.865%))
  Logic Levels:           0  
  Clock Path Skew:        -0.135ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.499ns
    Source Clock Delay      (SCD):    2.634ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.077ns (routing 0.391ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.216ns (routing 0.432ns, distribution 0.784ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.077     2.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X86Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y349        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.673 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[23]/Q
                         net (fo=1, routed)           0.072     2.745    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X87Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.216     2.499    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X87Y349        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[23].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_addr_strobe_lvl_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.039ns (33.665%)  route 0.077ns (66.335%))
  Logic Levels:           0  
  Clock Path Skew:        -0.120ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.509ns
    Source Clock Delay      (SCD):    2.629ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.391ns, distribution 0.681ns)
  Clock Net Delay (Destination): 1.226ns (routing 0.432ns, distribution 0.794ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.072     2.629    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_addr_strobe_lvl_riuclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y308        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.668 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_addr_strobe_lvl_riuclk_reg/Q
                         net (fo=2, routed)           0.077     2.745    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/D[0]
    SLICE_X88Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.226     2.509    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/SYNC[0].sync_reg_reg[1]_0
    SLICE_X88Y308        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_strobe_lvl_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.130ns  (logic 0.038ns (29.231%)  route 0.092ns (70.769%))
  Logic Levels:           0  
  Clock Path Skew:        -0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.486ns
    Source Clock Delay      (SCD):    2.617ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.060ns (routing 0.391ns, distribution 0.669ns)
  Clock Net Delay (Destination): 1.203ns (routing 0.432ns, distribution 0.771ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.060     2.617    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X87Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y296        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.655 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[4]/Q
                         net (fo=1, routed)           0.092     2.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[4]
    SLICE_X87Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.203     2.486    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X87Y296        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[4].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.301ns  (logic 0.080ns (26.575%)  route 0.221ns (73.425%))
  Logic Levels:           0  
  Clock Path Skew:        2.097ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.371ns
    Source Clock Delay      (SCD):    2.274ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.188ns (routing 0.171ns, distribution 1.017ns)
  Clock Net Delay (Destination): 1.737ns (routing 0.632ns, distribution 1.105ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.188     2.274    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y320        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.354 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.221     2.575    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X96Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.610    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.634 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.737     4.371    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X96Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.039ns (30.544%)  route 0.089ns (69.456%))
  Logic Levels:           0  
  Clock Path Skew:        1.214ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.505ns
    Source Clock Delay      (SCD):    1.291ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.674ns (routing 0.096ns, distribution 0.578ns)
  Clock Net Delay (Destination): 1.222ns (routing 0.432ns, distribution 0.790ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.674     1.291    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y320        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.330 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.089     1.419    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X96Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.283 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.222     2.505    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X96Y321        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Max Delay            78 Endpoints
Min Delay            86 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        1.119ns  (logic 0.079ns (7.061%)  route 1.040ns (92.939%))
  Logic Levels:           0  
  Clock Path Skew:        -3.529ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.982ns
    Source Clock Delay      (SCD):    7.511ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.846ns (routing 0.533ns, distribution 1.313ns)
  Clock Net Delay (Destination): 1.356ns (routing 0.578ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.846     7.511    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X101Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y332       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     7.590 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/Q
                         net (fo=20, routed)          1.040     8.630    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X81Y367        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.356     3.982    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X81Y367        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg1_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        1.119ns  (logic 0.079ns (7.061%)  route 1.040ns (92.939%))
  Logic Levels:           0  
  Clock Path Skew:        -3.529ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.982ns
    Source Clock Delay      (SCD):    7.511ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.846ns (routing 0.533ns, distribution 1.313ns)
  Clock Net Delay (Destination): 1.356ns (routing 0.578ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.846     7.511    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X101Y332       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y332       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     7.590 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/wrdata_rst_reg/Q
                         net (fo=20, routed)          1.040     8.630    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rst
    SLICE_X81Y367        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.356     3.982    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X81Y367        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.744ns  (logic 0.287ns (38.575%)  route 0.457ns (61.425%))
  Logic Levels:           0  
  Clock Path Skew:        -3.512ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.980ns
    Source Clock Delay      (SCD):    7.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.827ns (routing 0.533ns, distribution 1.294ns)
  Clock Net Delay (Destination): 1.354ns (routing 0.578ns, distribution 0.776ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.827     7.492    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X83Y363        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y363        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     7.779 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/O
                         net (fo=1, routed)           0.457     8.236    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[6]
    SLICE_X83Y362        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.354     3.980    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X83Y362        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.726ns  (logic 0.079ns (10.882%)  route 0.647ns (89.118%))
  Logic Levels:           0  
  Clock Path Skew:        -3.522ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.960ns
    Source Clock Delay      (SCD):    7.482ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.817ns (routing 0.533ns, distribution 1.284ns)
  Clock Net Delay (Destination): 1.334ns (routing 0.578ns, distribution 0.756ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.817     7.482    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y366        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     7.561 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[16]/Q
                         net (fo=2, routed)           0.647     8.208    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[16]
    SLICE_X89Y367        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.334     3.960    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X89Y367        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[16]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.700ns  (logic 0.304ns (43.429%)  route 0.396ns (56.571%))
  Logic Levels:           0  
  Clock Path Skew:        -3.506ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.986ns
    Source Clock Delay      (SCD):    7.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.827ns (routing 0.533ns, distribution 1.294ns)
  Clock Net Delay (Destination): 1.360ns (routing 0.578ns, distribution 0.782ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.827     7.492    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X83Y363        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y363        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     7.796 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMF_D1/O
                         net (fo=1, routed)           0.396     8.192    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[11]
    SLICE_X83Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.360     3.986    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X83Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[11]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.675ns  (logic 0.301ns (44.593%)  route 0.374ns (55.407%))
  Logic Levels:           0  
  Clock Path Skew:        -3.507ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.985ns
    Source Clock Delay      (SCD):    7.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.827ns (routing 0.533ns, distribution 1.294ns)
  Clock Net Delay (Destination): 1.359ns (routing 0.578ns, distribution 0.781ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.827     7.492    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X83Y363        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y363        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     7.793 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/O
                         net (fo=1, routed)           0.374     8.167    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[7]
    SLICE_X83Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.359     3.985    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X83Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[7]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.660ns  (logic 0.080ns (12.114%)  route 0.580ns (87.887%))
  Logic Levels:           0  
  Clock Path Skew:        -3.511ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.962ns
    Source Clock Delay      (SCD):    7.473ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.808ns (routing 0.533ns, distribution 1.275ns)
  Clock Net Delay (Destination): 1.336ns (routing 0.578ns, distribution 0.758ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.808     7.473    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y369        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y369        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     7.553 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/Q
                         net (fo=29, routed)          0.580     8.133    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp
    SLICE_X91Y373        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.336     3.962    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X91Y373        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.641ns  (logic 0.295ns (46.022%)  route 0.346ns (53.978%))
  Logic Levels:           0  
  Clock Path Skew:        -3.506ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.986ns
    Source Clock Delay      (SCD):    7.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.827ns (routing 0.533ns, distribution 1.294ns)
  Clock Net Delay (Destination): 1.360ns (routing 0.578ns, distribution 0.782ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.827     7.492    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X83Y363        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y363        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     7.787 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMG_D1/O
                         net (fo=1, routed)           0.346     8.133    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[13]
    SLICE_X83Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.360     3.986    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X83Y360        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.632ns  (logic 0.288ns (45.570%)  route 0.344ns (54.430%))
  Logic Levels:           0  
  Clock Path Skew:        -3.509ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.983ns
    Source Clock Delay      (SCD):    7.492ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.827ns (routing 0.533ns, distribution 1.294ns)
  Clock Net Delay (Destination): 1.357ns (routing 0.578ns, distribution 0.779ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.827     7.492    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X83Y363        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y363        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     7.780 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/O
                         net (fo=1, routed)           0.344     8.124    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[8]
    SLICE_X82Y362        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.357     3.983    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X82Y362        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[8]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.641ns  (logic 0.079ns (12.325%)  route 0.562ns (87.675%))
  Logic Levels:           0  
  Clock Path Skew:        -3.518ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.964ns
    Source Clock Delay      (SCD):    7.482ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.817ns (routing 0.533ns, distribution 1.284ns)
  Clock Net Delay (Destination): 1.338ns (routing 0.578ns, distribution 0.760ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.337     5.637    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.665 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.817     7.482    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y371        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     7.561 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/Q
                         net (fo=2, routed)           0.562     8.123    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[16]
    SLICE_X91Y373        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.207     2.602    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.626 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         1.338     3.964    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X91Y373        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[16]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.096ns  (logic 0.038ns (39.545%)  route 0.058ns (60.455%))
  Logic Levels:           0  
  Clock Path Skew:        0.025ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.223ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.005ns (routing 0.294ns, distribution 0.711ns)
  Clock Net Delay (Destination): 0.947ns (routing 0.390ns, distribution 0.557ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.005     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y372        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     2.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[6]/Q
                         net (fo=2, routed)           0.058     2.294    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[6]
    SLICE_X91Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.947     2.223    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X91Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[6]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.038ns (38.000%)  route 0.062ns (62.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.029ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.228ns
    Source Clock Delay      (SCD):    2.199ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.006ns (routing 0.294ns, distribution 0.712ns)
  Clock Net Delay (Destination): 0.952ns (routing 0.390ns, distribution 0.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.006     2.199    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y366        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     2.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[3]/Q
                         net (fo=2, routed)           0.062     2.299    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[3]
    SLICE_X89Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.952     2.228    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X89Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_ld_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.041ns (38.795%)  route 0.065ns (61.205%))
  Logic Levels:           0  
  Clock Path Skew:        0.018ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.215ns
    Source Clock Delay      (SCD):    2.197ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.004ns (routing 0.294ns, distribution 0.710ns)
  Clock Net Delay (Destination): 0.939ns (routing 0.390ns, distribution 0.549ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.004     2.197    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X94Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y371        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.238 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp_reg/Q
                         net (fo=5, routed)           0.065     2.303    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp
    SLICE_X94Y370        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_ld_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.939     2.215    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/clk
    SLICE_X94Y370        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/stat_reg_ld_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.040ns (38.007%)  route 0.065ns (61.993%))
  Logic Levels:           0  
  Clock Path Skew:        0.029ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.227ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.005ns (routing 0.294ns, distribution 0.711ns)
  Clock Net Delay (Destination): 0.951ns (routing 0.390ns, distribution 0.561ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.005     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y372        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     2.238 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[10]/Q
                         net (fo=2, routed)           0.065     2.303    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[10]
    SLICE_X91Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.951     2.227    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X91Y372        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[10]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.037ns (34.875%)  route 0.069ns (65.125%))
  Logic Levels:           0  
  Clock Path Skew:        0.030ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.228ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.005ns (routing 0.294ns, distribution 0.711ns)
  Clock Net Delay (Destination): 0.952ns (routing 0.390ns, distribution 0.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.005     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y366        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.235 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/Q
                         net (fo=2, routed)           0.069     2.304    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[7]
    SLICE_X89Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.952     2.228    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X89Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.040ns (38.955%)  route 0.063ns (61.045%))
  Logic Levels:           0  
  Clock Path Skew:        0.009ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.218ns
    Source Clock Delay      (SCD):    2.209ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.016ns (routing 0.294ns, distribution 0.722ns)
  Clock Net Delay (Destination): 0.942ns (routing 0.390ns, distribution 0.552ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.016     2.209    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X101Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y334       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     2.249 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.063     2.311    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in[1]
    SLICE_X100Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.942     2.218    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/clk
    SLICE_X100Y334       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.117ns  (logic 0.039ns (33.424%)  route 0.078ns (66.576%))
  Logic Levels:           0  
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.226ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.005ns (routing 0.294ns, distribution 0.711ns)
  Clock Net Delay (Destination): 0.950ns (routing 0.390ns, distribution 0.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.005     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X90Y371        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y371        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[27]/Q
                         net (fo=2, routed)           0.078     2.314    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[27]
    SLICE_X90Y370        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.950     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X90Y370        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[27]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.117ns  (logic 0.039ns (33.424%)  route 0.078ns (66.576%))
  Logic Levels:           0  
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.226ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.005ns (routing 0.294ns, distribution 0.711ns)
  Clock Net Delay (Destination): 0.950ns (routing 0.390ns, distribution 0.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.005     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y366        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[9]/Q
                         net (fo=2, routed)           0.078     2.314    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[9]
    SLICE_X89Y367        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.950     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X89Y367        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[9]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.038ns (32.290%)  route 0.080ns (67.710%))
  Logic Levels:           0  
  Clock Path Skew:        0.029ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.228ns
    Source Clock Delay      (SCD):    2.199ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.006ns (routing 0.294ns, distribution 0.712ns)
  Clock Net Delay (Destination): 0.952ns (routing 0.390ns, distribution 0.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.006     2.199    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X89Y366        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y366        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     2.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[4]/Q
                         net (fo=2, routed)           0.080     2.316    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[4]
    SLICE_X89Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.952     2.228    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X89Y365        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[4]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        0.028ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.226ns
    Source Clock Delay      (SCD):    2.198ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.005ns (routing 0.294ns, distribution 0.711ns)
  Clock Net Delay (Destination): 0.950ns (routing 0.390ns, distribution 0.560ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.711     1.176    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.193 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.005     2.198    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y362        FDCE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.081     2.318    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.950     2.226    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X88Y362        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Max Delay             0 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.040ns (40.404%)  route 0.059ns (59.596%))
  Logic Levels:           0  
  Clock Path Skew:        -0.401ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.214ns
    Source Clock Delay      (SCD):    2.615ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.068ns (routing 0.385ns, distribution 0.683ns)
  Clock Net Delay (Destination): 0.938ns (routing 0.390ns, distribution 0.548ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.068     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     2.655 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.059     2.714    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X83Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.938     2.214    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X83Y357        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        -0.407ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.215ns
    Source Clock Delay      (SCD):    2.623ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.076ns (routing 0.385ns, distribution 0.691ns)
  Clock Net Delay (Destination): 0.940ns (routing 0.390ns, distribution 0.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.076     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X84Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y354        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.662 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.058     2.720    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.940     2.215    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.039ns (32.773%)  route 0.080ns (67.227%))
  Logic Levels:           0  
  Clock Path Skew:        -0.397ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.218ns
    Source Clock Delay      (SCD):    2.615ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.068ns (routing 0.385ns, distribution 0.683ns)
  Clock Net Delay (Destination): 0.942ns (routing 0.390ns, distribution 0.552ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.068     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.654 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.080     2.734    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X83Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.942     2.218    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X83Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        -0.417ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.203ns
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.073ns (routing 0.385ns, distribution 0.688ns)
  Clock Net Delay (Destination): 0.927ns (routing 0.390ns, distribution 0.537ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.073     2.620    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X86Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y358        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.085     2.744    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X85Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.927     2.203    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X85Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.410ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.215ns
    Source Clock Delay      (SCD):    2.626ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.079ns (routing 0.385ns, distribution 0.694ns)
  Clock Net Delay (Destination): 0.940ns (routing 0.390ns, distribution 0.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.079     2.626    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X84Y355        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y355        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.665 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.081     2.746    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.940     2.215    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X84Y356        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.165ns  (logic 0.039ns (23.636%)  route 0.126ns (76.364%))
  Logic Levels:           0  
  Clock Path Skew:        -0.404ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.211ns
    Source Clock Delay      (SCD):    2.615ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.068ns (routing 0.385ns, distribution 0.683ns)
  Clock Net Delay (Destination): 0.935ns (routing 0.390ns, distribution 0.545ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.068     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.654 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.126     2.780    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.935     2.211    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.182ns  (logic 0.039ns (21.429%)  route 0.143ns (78.571%))
  Logic Levels:           0  
  Clock Path Skew:        -0.420ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.203ns
    Source Clock Delay      (SCD):    2.623ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.076ns (routing 0.385ns, distribution 0.691ns)
  Clock Net Delay (Destination): 0.927ns (routing 0.390ns, distribution 0.537ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.076     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X85Y354        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y354        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.662 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.143     2.805    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.927     2.203    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.203ns  (logic 0.041ns (20.229%)  route 0.162ns (79.771%))
  Logic Levels:           0  
  Clock Path Skew:        -0.411ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.203ns
    Source Clock Delay      (SCD):    2.614ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.067ns (routing 0.385ns, distribution 0.682ns)
  Clock Net Delay (Destination): 0.927ns (routing 0.390ns, distribution 0.537ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.067     2.614    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X82Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y358        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.655 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.162     2.817    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.927     2.203    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/CLK
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.216ns  (logic 0.039ns (18.056%)  route 0.177ns (81.944%))
  Logic Levels:           0  
  Clock Path Skew:        -0.412ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.203ns
    Source Clock Delay      (SCD):    2.615ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.068ns (routing 0.385ns, distribution 0.683ns)
  Clock Net Delay (Destination): 0.927ns (routing 0.390ns, distribution 0.537ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.068     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.654 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.177     2.831    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.927     2.203    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X85Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.236ns  (logic 0.040ns (16.949%)  route 0.196ns (83.051%))
  Logic Levels:           0  
  Clock Path Skew:        -0.399ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.216ns
    Source Clock Delay      (SCD):    2.615ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.068ns (routing 0.385ns, distribution 0.683ns)
  Clock Net Delay (Destination): 0.940ns (routing 0.390ns, distribution 0.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.068     2.615    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[1]
    SLICE_X84Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y358        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.655 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.196     2.851    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X82Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.159     1.257    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y118        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.276 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y5 (CLOCK_ROOT)    net (fo=568, routed)         0.940     2.216    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X82Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Max Delay             0 Endpoints
Min Delay            35 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.106ns  (logic 0.039ns (36.792%)  route 0.067ns (63.208%))
  Logic Levels:           0  
  Clock Path Skew:        -0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.511ns
    Source Clock Delay      (SCD):    2.619ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.385ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.217ns (routing 0.439ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.072     2.619    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X86Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y312        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.658 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[14]/Q
                         net (fo=1, routed)           0.067     2.725    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[14]
    SLICE_X86Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.217     2.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X86Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[14].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.039ns (32.773%)  route 0.080ns (67.227%))
  Logic Levels:           0  
  Clock Path Skew:        -0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.512ns
    Source Clock Delay      (SCD):    2.619ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.385ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.218ns (routing 0.439ns, distribution 0.779ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.072     2.619    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X85Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y313        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.658 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/Q
                         net (fo=1, routed)           0.080     2.738    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[0]
    SLICE_X84Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.218     2.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X84Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.040ns (32.787%)  route 0.082ns (67.213%))
  Logic Levels:           0  
  Clock Path Skew:        -0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.516ns
    Source Clock Delay      (SCD):    2.619ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.385ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.222ns (routing 0.439ns, distribution 0.783ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.072     2.619    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X85Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y313        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[2]/Q
                         net (fo=1, routed)           0.082     2.741    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[2]
    SLICE_X85Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.222     2.516    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X85Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (31.967%)  route 0.083ns (68.033%))
  Logic Levels:           0  
  Clock Path Skew:        -0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.512ns
    Source Clock Delay      (SCD):    2.620ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.073ns (routing 0.385ns, distribution 0.688ns)
  Clock Net Delay (Destination): 1.218ns (routing 0.439ns, distribution 0.779ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.073     2.620    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X84Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y310        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/Q
                         net (fo=1, routed)           0.083     2.742    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[5]
    SLICE_X84Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.218     2.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X84Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[16].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.040ns (32.000%)  route 0.085ns (68.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.511ns
    Source Clock Delay      (SCD):    2.619ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.385ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.217ns (routing 0.439ns, distribution 0.778ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.072     2.619    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X86Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y312        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     2.659 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[16]/Q
                         net (fo=1, routed)           0.085     2.744    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[16]
    SLICE_X86Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[16].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.217     2.511    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X86Y313        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[16].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.231%)  route 0.082ns (67.769%))
  Logic Levels:           0  
  Clock Path Skew:        -0.113ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.513ns
    Source Clock Delay      (SCD):    2.626ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.079ns (routing 0.385ns, distribution 0.694ns)
  Clock Net Delay (Destination): 1.219ns (routing 0.439ns, distribution 0.780ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.079     2.626    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X88Y314        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y314        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.665 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/Q
                         net (fo=1, routed)           0.082     2.747    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[13]
    SLICE_X88Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.219     2.513    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X88Y316        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.039ns (29.771%)  route 0.092ns (70.229%))
  Logic Levels:           0  
  Clock Path Skew:        -0.102ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.517ns
    Source Clock Delay      (SCD):    2.619ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.385ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.223ns (routing 0.439ns, distribution 0.784ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.072     2.619    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X87Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y318        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.658 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[19]/Q
                         net (fo=1, routed)           0.092     2.750    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[19]
    SLICE_X87Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.223     2.517    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X87Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[19].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        -0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.513ns
    Source Clock Delay      (SCD):    2.621ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.074ns (routing 0.385ns, distribution 0.689ns)
  Clock Net Delay (Destination): 1.219ns (routing 0.439ns, distribution 0.780ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.074     2.621    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X84Y307        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y307        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.660 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[7]/Q
                         net (fo=1, routed)           0.090     2.750    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[7]
    SLICE_X84Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.219     2.513    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X84Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        -0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.512ns
    Source Clock Delay      (SCD):    2.619ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.385ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.218ns (routing 0.439ns, distribution 0.779ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.072     2.619    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X86Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y312        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.658 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[18]/Q
                         net (fo=1, routed)           0.093     2.751    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[18]
    SLICE_X86Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.218     2.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X86Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[18].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.039ns (29.104%)  route 0.095ns (70.896%))
  Logic Levels:           0  
  Clock Path Skew:        -0.107ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.512ns
    Source Clock Delay      (SCD):    2.619ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.072ns (routing 0.385ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.218ns (routing 0.439ns, distribution 0.779ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.072     2.619    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X86Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y312        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.658 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[10]/Q
                         net (fo=1, routed)           0.095     2.753    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[10]
    SLICE_X86Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.218     2.512    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X86Y312        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[10].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay           486 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.666ns  (logic 0.079ns (11.867%)  route 0.587ns (88.133%))
  Logic Levels:           0  
  Clock Path Skew:        0.200ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.385ns
    Source Clock Delay      (SCD):    4.185ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.972ns (routing 0.709ns, distribution 1.263ns)
  Clock Net Delay (Destination): 1.738ns (routing 0.644ns, distribution 1.094ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.972     4.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X95Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y350        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     4.264 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.587     4.851    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X92Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.738     4.385    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X92Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.337ns  (logic 0.081ns (24.036%)  route 0.256ns (75.964%))
  Logic Levels:           0  
  Clock Path Skew:        0.206ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.393ns
    Source Clock Delay      (SCD):    4.187ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.974ns (routing 0.709ns, distribution 1.265ns)
  Clock Net Delay (Destination): 1.746ns (routing 0.644ns, distribution 1.102ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     2.185    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.213 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.974     4.187    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X95Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y358        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     4.268 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.256     4.524    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X94Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.746     4.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X94Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.145ns  (logic 0.040ns (27.586%)  route 0.105ns (72.414%))
  Logic Levels:           0  
  Clock Path Skew:        -0.121ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.522ns
    Source Clock Delay      (SCD):    2.643ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.086ns (routing 0.391ns, distribution 0.695ns)
  Clock Net Delay (Destination): 1.228ns (routing 0.439ns, distribution 0.789ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.086     2.643    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X95Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y358        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.683 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.105     2.788    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X94Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.228     2.522    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X94Y358        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.298ns  (logic 0.039ns (13.082%)  route 0.259ns (86.918%))
  Logic Levels:           0  
  Clock Path Skew:        -0.128ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.514ns
    Source Clock Delay      (SCD):    2.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.085ns (routing 0.391ns, distribution 0.694ns)
  Clock Net Delay (Destination): 1.220ns (routing 0.439ns, distribution 0.781ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.085     2.642    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X95Y350        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y350        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.681 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.259     2.940    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X92Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.220     2.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X92Y359        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.309ns  (logic 0.038ns (12.310%)  route 0.271ns (87.690%))
  Logic Levels:           0  
  Clock Path Skew:        -0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.582ns
    Source Clock Delay      (SCD):    2.635ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.078ns (routing 0.391ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.288ns (routing 0.439ns, distribution 0.849ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.078     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y320        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.673 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/Q
                         net (fo=22, routed)          0.271     2.944    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_4[0]
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.288     2.582    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y42
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.309ns  (logic 0.038ns (12.310%)  route 0.271ns (87.690%))
  Logic Levels:           0  
  Clock Path Skew:        -0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.578ns
    Source Clock Delay      (SCD):    2.635ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.078ns (routing 0.391ns, distribution 0.687ns)
  Clock Net Delay (Destination): 1.284ns (routing 0.439ns, distribution 0.845ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.078     2.635    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y320        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.673 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_addr_reg[0]/Q
                         net (fo=22, routed)          0.271     2.944    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_6[0]
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_ADDR[0]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.284     2.578    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y43
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[9].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.347ns  (logic 0.038ns (10.961%)  route 0.309ns (89.039%))
  Logic Levels:           0  
  Clock Path Skew:        -0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.582ns
    Source Clock Delay      (SCD):    2.637ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.080ns (routing 0.391ns, distribution 0.689ns)
  Clock Net Delay (Destination): 1.288ns (routing 0.439ns, distribution 0.849ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.080     2.637    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y351        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.675 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/Q
                         net (fo=22, routed)          0.309     2.984    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[1]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[1]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.288     2.582    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.348ns  (logic 0.038ns (10.929%)  route 0.310ns (89.071%))
  Logic Levels:           0  
  Clock Path Skew:        -0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.586ns
    Source Clock Delay      (SCD):    2.637ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.080ns (routing 0.391ns, distribution 0.689ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.439ns, distribution 0.853ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.080     2.637    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y351        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y351        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.675 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[1]/Q
                         net (fo=22, routed)          0.310     2.985    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[1]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[1]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.292     2.586    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.364ns  (logic 0.039ns (10.724%)  route 0.325ns (89.276%))
  Logic Levels:           0  
  Clock Path Skew:        -0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.582ns
    Source Clock Delay      (SCD):    2.634ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.077ns (routing 0.391ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.288ns (routing 0.439ns, distribution 0.849ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.077     2.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y338        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.673 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=22, routed)          0.325     2.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[12]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.288     2.582    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.364ns  (logic 0.039ns (10.724%)  route 0.325ns (89.276%))
  Logic Levels:           0  
  Clock Path Skew:        -0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.586ns
    Source Clock Delay      (SCD):    2.634ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.077ns (routing 0.391ns, distribution 0.686ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.439ns, distribution 0.853ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.077     2.634    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y338        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y338        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.673 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=22, routed)          0.325     2.998    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[12]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.292     2.586    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.360ns  (logic 0.040ns (11.121%)  route 0.320ns (88.879%))
  Logic Levels:           0  
  Clock Path Skew:        -0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.582ns
    Source Clock Delay      (SCD):    2.639ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.082ns (routing 0.391ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.288ns (routing 0.439ns, distribution 0.849ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.082     2.639    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y352        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.679 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/Q
                         net (fo=22, routed)          0.320     2.999    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[3]
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.288     2.582    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y46
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.361ns  (logic 0.040ns (11.090%)  route 0.321ns (88.910%))
  Logic Levels:           0  
  Clock Path Skew:        -0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.586ns
    Source Clock Delay      (SCD):    2.639ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.082ns (routing 0.391ns, distribution 0.691ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.439ns, distribution 0.853ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     1.540    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.557 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.082     2.639    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y352        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y352        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     2.679 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[3]/Q
                         net (fo=22, routed)          0.321     3.000    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[3]
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.292     2.586    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y47
                         BITSLICE_CONTROL                             r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[11].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  sys_clk_ddr4_clk_p
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.401ns  (logic 0.080ns (19.948%)  route 0.321ns (80.052%))
  Logic Levels:           0  
  Clock Path Skew:        2.107ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.381ns
    Source Clock Delay      (SCD):    2.274ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.188ns (routing 0.171ns, distribution 1.017ns)
  Clock Net Delay (Destination): 1.734ns (routing 0.644ns, distribution 1.090ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.188     2.274    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y320        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.354 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.321     2.675    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X93Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.734     4.381    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X93Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.282ns  (logic 0.081ns (28.723%)  route 0.201ns (71.277%))
  Logic Levels:           0  
  Clock Path Skew:        2.111ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.375ns
    Source Clock Delay      (SCD):    2.264ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.178ns (routing 0.171ns, distribution 1.007ns)
  Clock Net Delay (Destination): 1.728ns (routing 0.644ns, distribution 1.084ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.178     2.264    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y319        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.345 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.201     2.546    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X95Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.850     1.765    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     2.395 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     2.623    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.647 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.728     4.375    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X95Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        1.223ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.508ns
    Source Clock Delay      (SCD):    1.285ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.668ns (routing 0.096ns, distribution 0.572ns)
  Clock Net Delay (Destination): 1.214ns (routing 0.439ns, distribution 0.775ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.668     1.285    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y319        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.325 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.079     1.404    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X95Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.214     2.508    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X95Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.174ns  (logic 0.039ns (22.455%)  route 0.135ns (77.545%))
  Logic Levels:           0  
  Clock Path Skew:        1.223ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.514ns
    Source Clock Delay      (SCD):    1.291ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.674ns (routing 0.096ns, distribution 0.578ns)
  Clock Net Delay (Destination): 1.220ns (routing 0.439ns, distribution 0.781ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.674     1.291    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y320        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.330 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.135     1.465    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X93Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.606     1.393    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     1.098 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     1.275    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y107        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.294 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=1736, routed)        1.220     2.514    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X93Y318        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  sys_clk_ddr4_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (recovery check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.383ns  (logic 0.076ns (19.843%)  route 0.307ns (80.157%))
  Logic Levels:           0  
  Clock Path Skew:        -0.741ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.911ns
    Source Clock Delay      (SCD):    2.652ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.426ns (routing 0.777ns, distribution 1.649ns)
  Clock Net Delay (Destination): 0.996ns (routing 0.155ns, distribution 0.841ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.426     2.652    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y348        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y348        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.728 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.307     3.035    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y350        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.996     1.911    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y350        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (recovery check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.383ns  (logic 0.076ns (19.843%)  route 0.307ns (80.157%))
  Logic Levels:           0  
  Clock Path Skew:        -0.741ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.911ns
    Source Clock Delay      (SCD):    2.652ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.426ns (routing 0.777ns, distribution 1.649ns)
  Clock Net Delay (Destination): 0.996ns (routing 0.155ns, distribution 0.841ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.426     2.652    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y348        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y348        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.728 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.307     3.035    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y350        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.996     1.911    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y350        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (removal check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.038ns (21.111%)  route 0.142ns (78.889%))
  Logic Levels:           0  
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.449ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.329ns (routing 0.421ns, distribution 0.908ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.329     1.449    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y348        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y348        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.487 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.142     1.629    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y350        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y350        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (removal check against rising-edge clock sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.038ns (21.111%)  route 0.142ns (78.889%))
  Logic Levels:           0  
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.529ns
    Source Clock Delay      (SCD):    1.449ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.329ns (routing 0.421ns, distribution 0.908ns)
  Clock Net Delay (Destination): 0.742ns (routing 0.108ns, distribution 0.634ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.329     1.449    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X83Y348        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y348        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.487 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.142     1.629    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X81Y350        FDPE                                         f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.742     1.529    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X81Y350        FDPE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  

Max Delay             6 Endpoints
Min Delay             6 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.898ns  (logic 0.028ns (0.966%)  route 2.870ns (99.034%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.672     7.898    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.867ns  (logic 0.028ns (0.977%)  route 2.839ns (99.023%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.641     7.867    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.856ns  (logic 0.028ns (0.980%)  route 2.828ns (99.020%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.630     7.856    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.846ns  (logic 0.028ns (0.984%)  route 2.818ns (99.016%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.620     7.846    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.812ns  (logic 0.028ns (0.996%)  route 2.784ns (99.004%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.586     7.812    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.796ns  (logic 0.028ns (1.001%)  route 2.768ns (98.999%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.570     7.796    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.510ns  (logic 0.017ns (1.126%)  route 1.493ns (98.874%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.390     1.510    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y3           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.521ns  (logic 0.017ns (1.118%)  route 1.504ns (98.882%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.401     1.521    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y2           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.536ns  (logic 0.017ns (1.107%)  route 1.519ns (98.893%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.416     1.536    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y0           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.541ns  (logic 0.017ns (1.103%)  route 1.524ns (98.897%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.421     1.541    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y1           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.549ns  (logic 0.017ns (1.097%)  route 1.532ns (98.903%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.429     1.549    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSDAC_X0Y1           HSDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.559ns  (logic 0.017ns (1.090%)  route 1.542ns (98.910%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.439     1.559    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    HSADC_X0Y0           HSADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_pl_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.321ns  (logic 0.927ns (39.927%)  route 1.394ns (60.073%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.941ns (routing 0.696ns, distribution 1.245ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.572     0.672 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.722    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.722 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     1.058    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.086 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.964     2.050    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     1.923 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.168    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.196 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.941     4.137    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y310        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     4.217 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           1.394     5.611    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    A17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.847     6.457 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     6.457    ddr4_pl_reset_n
    A17                                                               r  ddr4_pl_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_pl_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.098ns  (logic 0.459ns (41.811%)  route 0.639ns (58.189%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.071ns (routing 0.385ns, distribution 0.686ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.330     0.409 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.449    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.449 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.151     0.600    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.617 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
                         net (fo=18, routed)          0.537     1.154    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y4            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.384 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.530    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.547 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y3 (CLOCK_ROOT)    net (fo=41413, routed)       1.071     2.618    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[10]
    SLICE_X81Y310        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y310        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.657 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           0.639     3.296    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    A17                  OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.420     3.716 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     3.716    ddr4_pl_reset_n
    A17                                                               r  ddr4_pl_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_adc0_x2_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.679ns  (logic 0.123ns (4.591%)  route 2.556ns (95.409%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 2.724ns (routing 1.417ns, distribution 1.307ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           2.506     2.506    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X55Y251        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     2.629 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.050     2.679    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X55Y251        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          2.549     2.935    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     3.565 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.214     3.779    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.803 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       2.724     6.527    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X55Y251        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_adc0_x2_0  {rise@0.000ns fall@0.976ns period=1.953ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.359ns  (logic 0.050ns (3.679%)  route 1.309ns (96.321%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.122ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.073ns
    Phase Error              (PE):    0.077ns
  Clock Net Delay (Destination): 1.870ns (routing 0.956ns, distribution 0.914ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y7            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.292     1.292    d_1_i/rst_adc0_x2/U0/EXT_LPF/dcm_locked
    SLICE_X55Y251        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     1.342 r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.017     1.359    d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int0__0
    SLICE_X55Y251        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_adc0_x2_0 rise edge)
                                                      0.000     0.000 r  
    HSADC_X0Y0           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV2_MUX
    HSADC_X0Y0           HSADC (Prop_HSADC_INTERNAL_FBRC_DIV2_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/CLK_ADC
                         net (fo=2, routed)           0.170     0.270    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt_0
    BUFG_GT_X1Y23        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.352 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc0_bufg_gt/O
                         net (fo=35, routed)          1.730     2.082    d_1_i/clk_adc0_x2/inst/clk_in1
    MMCM_X0Y7            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.787 r  d_1_i/clk_adc0_x2/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.165     1.952    d_1_i/clk_adc0_x2/inst/clk_out1_d_1_clk_adc0_x2_0
    BUFGCE_X0Y170        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.971 r  d_1_i/clk_adc0_x2/inst/clkout1_buf/O
    X3Y3 (CLOCK_ROOT)    net (fo=44852, routed)       1.870     3.841    d_1_i/rst_adc0_x2/U0/EXT_LPF/slowest_sync_clk
    SLICE_X55Y251        FDRE                                         r  d_1_i/rst_adc0_x2/U0/EXT_LPF/lpf_int_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             3 Endpoints
Min Delay             3 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.517ns  (logic 0.642ns (18.264%)  route 2.875ns (81.736%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        5.442ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.442ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.369ns (routing 1.464ns, distribution 0.905ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L15                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    L15                  INBUF (Prop_INBUF_HPIOB_M_PAD_O)
                                                      0.642     0.642 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.642    PMOD1_1_LS_IBUF_inst/OUT
    L15                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.642 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           2.875     3.517    d_1_i/qick_processor_0/inst/proc_stop_i
    SLICE_X27Y244        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.369     5.442    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X27Y244        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.179ns  (logic 0.643ns (20.219%)  route 2.536ns (79.781%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        5.445ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    5.445ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.372ns (routing 1.464ns, distribution 0.908ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.643     0.643 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.643    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.643 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           2.536     3.179    d_1_i/qick_processor_0/inst/proc_start_i
    SLICE_X30Y249        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.372     5.445    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X30Y249        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.093ns  (logic 0.146ns (6.976%)  route 1.947ns (93.024%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 2.500ns (routing 1.464ns, distribution 1.036ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y5            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.897     1.897    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X55Y257        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     2.043 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.050     2.093    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X55Y257        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       2.022     2.204    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.834 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     3.049    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     3.073 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        2.500     5.573    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X55Y257        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.043ns  (logic 0.059ns (5.657%)  route 0.984ns (94.343%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.717ns (routing 0.978ns, distribution 0.739ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y5            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           0.967     0.967    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X55Y257        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.059     1.026 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.017     1.043    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X55Y257        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.717     3.124    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X55Y257        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C

Slack:                    inf
  Source:                 PMOD1_0_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.335ns  (logic 0.194ns (14.557%)  route 1.141ns (85.443%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        3.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.040ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.633ns (routing 0.978ns, distribution 0.655ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L14                                               0.000     0.000 r  PMOD1_0_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_0_LS_IBUF_inst/I
    L14                  INBUF (Prop_INBUF_HPIOB_S_PAD_O)
                                                      0.194     0.194 r  PMOD1_0_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_0_LS_IBUF_inst/OUT
    L14                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_S_I_O)
                                                      0.000     0.194 r  PMOD1_0_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           1.141     1.335    d_1_i/qick_processor_0/inst/proc_start_i
    SLICE_X30Y249        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.633     3.040    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X30Y249        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_start_cdc_reg/C

Slack:                    inf
  Source:                 PMOD1_1_LS
                            (input port)
  Destination:            d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.491ns  (logic 0.194ns (13.019%)  route 1.297ns (86.981%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        3.039ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.039ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.632ns (routing 0.978ns, distribution 0.654ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L15                                               0.000     0.000 r  PMOD1_1_LS (IN)
                         net (fo=0)                   0.000     0.000    PMOD1_1_LS_IBUF_inst/I
    L15                  INBUF (Prop_INBUF_HPIOB_M_PAD_O)
                                                      0.194     0.194 r  PMOD1_1_LS_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.194    PMOD1_1_LS_IBUF_inst/OUT
    L15                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.194 r  PMOD1_1_LS_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           1.297     1.491    d_1_i/qick_processor_0/inst/proc_stop_i
    SLICE_X27Y244        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=71812, routed)       1.370     1.517    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y5            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.222 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.388    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y123        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.407 r  d_1_i/clk_core/inst/clkout1_buf/O
    X1Y3 (CLOCK_ROOT)    net (fo=3619, routed)        1.632     3.039    d_1_i/qick_processor_0/inst/c_clk_i
    SLICE_X27Y244        FDRE                                         r  d_1_i/qick_processor_0/inst/proc_stop_cdc_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.159ns  (logic 0.434ns (10.436%)  route 3.725ns (89.564%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[0]
                         net (fo=2, routed)           2.134     2.134    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[0]
    SLICE_X108Y104       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.149     2.283 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_28/O
                         net (fo=1, routed)           0.566     2.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_28_n_0
    SLICE_X103Y104       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.152     3.001 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_8/O
                         net (fo=1, routed)           0.387     3.388    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_8_n_0
    SLICE_X106Y104       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.096     3.484 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_2/O
                         net (fo=1, routed)           0.566     4.050    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_2_n_0
    SLICE_X110Y98        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     4.087 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.072     4.159    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.030ns  (logic 0.466ns (11.563%)  route 3.564ns (88.437%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.291ns (routing 0.703ns, distribution 1.588ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           2.095     2.095    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[1]
    SLICE_X108Y106       LUT4 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.147     2.242 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_55/O
                         net (fo=1, routed)           0.601     2.843    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_55_n_0
    SLICE_X103Y104       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     2.933 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_29/O
                         net (fo=1, routed)           0.100     3.033    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_29_n_0
    SLICE_X104Y104       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.090     3.123 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_8/O
                         net (fo=1, routed)           0.237     3.360    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_8_n_0
    SLICE_X107Y103       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     3.411 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_2/O
                         net (fo=1, routed)           0.465     3.876    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_2_n_0
    SLICE_X110Y98        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.088     3.964 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.066     4.030    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.291     2.473    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.760ns  (logic 0.465ns (12.368%)  route 3.295ns (87.632%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.300ns (routing 0.703ns, distribution 1.597ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[2]
                         net (fo=2, routed)           2.393     2.393    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[2]
    SLICE_X104Y106       LUT4 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.088     2.481 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_76/O
                         net (fo=1, routed)           0.082     2.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_76_n_0
    SLICE_X104Y105       LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.051     2.614 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_54/O
                         net (fo=1, routed)           0.085     2.699    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_54_n_0
    SLICE_X105Y105       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.749 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_23/O
                         net (fo=1, routed)           0.238     2.987    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_23_n_0
    SLICE_X106Y102       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.124     3.111 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6/O
                         net (fo=1, routed)           0.439     3.550    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6_n_0
    SLICE_X113Y97        LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.152     3.702 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.058     3.760    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.300     2.482    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.614ns  (logic 0.437ns (12.092%)  route 3.177ns (87.908%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.292ns (routing 0.703ns, distribution 1.589ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[7]
                         net (fo=1, routed)           2.476     2.476    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[7]
    SLICE_X105Y104       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     2.622 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_13/O
                         net (fo=1, routed)           0.051     2.673    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_13_n_0
    SLICE_X105Y104       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.146     2.819 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3/O
                         net (fo=1, routed)           0.578     3.397    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3_n_0
    SLICE_X110Y99        LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.145     3.542 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.072     3.614    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.292     2.474    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.591ns  (logic 0.346ns (9.634%)  route 3.245ns (90.366%))
  Logic Levels:           5  (LUT4=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.254ns (routing 0.703ns, distribution 1.551ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[3]
                         net (fo=2, routed)           2.411     2.411    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[3]
    SLICE_X104Y104       LUT4 (Prop_A6LUT_SLICEM_I0_O)
                                                      0.100     2.511 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_69/O
                         net (fo=1, routed)           0.043     2.554    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_69_n_0
    SLICE_X104Y104       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.037     2.591 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_32/O
                         net (fo=1, routed)           0.132     2.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_32_n_0
    SLICE_X105Y105       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.036     2.759 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_8/O
                         net (fo=1, routed)           0.322     3.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_8_n_0
    SLICE_X106Y102       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     3.131 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2/O
                         net (fo=1, routed)           0.271     3.402    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_2_n_0
    SLICE_X107Y95        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     3.525 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.066     3.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X107Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.254     2.436    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.254ns  (logic 0.260ns (7.990%)  route 2.994ns (92.010%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.243ns (routing 0.703ns, distribution 1.540ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y1           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[4]
                         net (fo=1, routed)           2.283     2.283    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac1_common_stat[4]
    SLICE_X103Y106       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.373 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_32/O
                         net (fo=1, routed)           0.094     2.467    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_32_n_0
    SLICE_X103Y105       LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.100     2.567 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_18/O
                         net (fo=1, routed)           0.280     2.847    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_18_n_0
    SLICE_X106Y105       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.035     2.882 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_6/O
                         net (fo=1, routed)           0.287     3.169    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_6_n_0
    SLICE_X106Y95        LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     3.204 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.050     3.254    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X106Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.243     2.425    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.240ns  (logic 0.350ns (10.802%)  route 2.890ns (89.198%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.245ns (routing 0.703ns, distribution 1.542ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           2.023     2.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[5]
    SLICE_X105Y103       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.098     2.121 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_21/O
                         net (fo=1, routed)           0.203     2.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_21_n_0
    SLICE_X103Y103       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.100     2.424 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_7/O
                         net (fo=1, routed)           0.151     2.575    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_7_n_0
    SLICE_X103Y103       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.053     2.628 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2/O
                         net (fo=1, routed)           0.464     3.092    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2_n_0
    SLICE_X106Y97        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.099     3.191 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.049     3.240    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       2.245     2.427    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.723ns  (logic 0.139ns (19.225%)  route 0.584ns (80.775%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[0]
                         net (fo=1, routed)           0.261     0.261    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[0]
    SLICE_X113Y88        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.051     0.312 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_56/O
                         net (fo=1, routed)           0.105     0.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_56_n_0
    SLICE_X110Y88        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.023     0.440 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_25/O
                         net (fo=1, routed)           0.107     0.547    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_25_n_0
    SLICE_X110Y93        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.015     0.562 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_6/O
                         net (fo=1, routed)           0.085     0.647    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_6_n_0
    SLICE_X110Y98        LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.050     0.697 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.026     0.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.735ns  (logic 0.128ns (17.415%)  route 0.607ns (82.585%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.586ns (routing 0.472ns, distribution 1.114ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[7]
                         net (fo=1, routed)           0.224     0.224    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[7]
    SLICE_X113Y88        LUT5 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.014     0.238 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_28/O
                         net (fo=1, routed)           0.162     0.400    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_28_n_0
    SLICE_X110Y90        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.059     0.459 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_19/O
                         net (fo=1, routed)           0.021     0.480    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_19_n_0
    SLICE_X110Y90        LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.014     0.494 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6/O
                         net (fo=1, routed)           0.174     0.668    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6_n_0
    SLICE_X110Y99        LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.041     0.709 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.026     0.735    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.586     1.733    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y99        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.758ns  (logic 0.165ns (21.768%)  route 0.593ns (78.232%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.593ns (routing 0.472ns, distribution 1.121ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[2]
                         net (fo=1, routed)           0.254     0.254    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[2]
    SLICE_X113Y88        LUT5 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.050     0.304 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_45/O
                         net (fo=1, routed)           0.156     0.460    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_45_n_0
    SLICE_X111Y92        LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.040     0.500 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_20/O
                         net (fo=1, routed)           0.082     0.582    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_20_n_0
    SLICE_X111Y97        LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.040     0.622 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_5/O
                         net (fo=1, routed)           0.080     0.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_5_n_0
    SLICE_X113Y97        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     0.737 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.021     0.758    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.593     1.740    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X113Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.818ns  (logic 0.086ns (10.513%)  route 0.732ns (89.487%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.550ns (routing 0.472ns, distribution 1.078ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[4]
                         net (fo=1, routed)           0.262     0.262    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[4]
    SLICE_X112Y88        LUT5 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.022     0.284 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_23/O
                         net (fo=1, routed)           0.023     0.307    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_23_n_0
    SLICE_X112Y88        LUT5 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.014     0.321 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_12/O
                         net (fo=1, routed)           0.227     0.548    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_12_n_0
    SLICE_X114Y91        LUT6 (Prop_B6LUT_SLICEL_I5_O)
                                                      0.015     0.563 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3/O
                         net (fo=1, routed)           0.203     0.766    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3_n_0
    SLICE_X106Y95        LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.035     0.801 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.017     0.818    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X106Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.550     1.697    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.821ns  (logic 0.139ns (16.931%)  route 0.682ns (83.069%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.561ns (routing 0.472ns, distribution 1.089ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[3]
                         net (fo=1, routed)           0.329     0.329    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[3]
    SLICE_X111Y89        LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.014     0.343 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_61/O
                         net (fo=1, routed)           0.068     0.411    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_61_n_0
    SLICE_X111Y90        LUT5 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     0.446 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_25/O
                         net (fo=1, routed)           0.025     0.471    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_25_n_0
    SLICE_X111Y90        LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.050     0.521 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_6/O
                         net (fo=1, routed)           0.236     0.757    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_6_n_0
    SLICE_X107Y95        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.040     0.797 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.024     0.821    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X107Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.561     1.708    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y95        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.831ns  (logic 0.137ns (16.480%)  route 0.694ns (83.520%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.585ns (routing 0.472ns, distribution 1.113ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSADC_X0Y1           HSADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           0.316     0.316    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/adc1_common_stat[1]
    SLICE_X113Y92        LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.022     0.338 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_40/O
                         net (fo=1, routed)           0.166     0.504    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_40_n_0
    SLICE_X110Y89        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.051     0.555 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_17/O
                         net (fo=1, routed)           0.111     0.666    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_17_n_0
    SLICE_X110Y94        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.050     0.716 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4/O
                         net (fo=1, routed)           0.077     0.793    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4_n_0
    SLICE_X110Y98        LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.014     0.807 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.024     0.831    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.585     1.732    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X110Y98        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.618ns  (logic 0.145ns (8.962%)  route 1.473ns (91.038%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.552ns (routing 0.472ns, distribution 1.080ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    HSDAC_X0Y0           HSDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[5]
                         net (fo=1, routed)           1.062     1.062    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_common_stat[5]
    SLICE_X105Y103       LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.041     1.103 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_21/O
                         net (fo=1, routed)           0.105     1.208    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_21_n_0
    SLICE_X103Y103       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.040     1.248 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_7/O
                         net (fo=1, routed)           0.078     1.326    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_7_n_0
    SLICE_X103Y103       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.023     1.349 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2/O
                         net (fo=1, routed)           0.212     1.561    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_2_n_0
    SLICE_X106Y97        LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.041     1.602 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.016     1.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y68        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=71812, routed)       1.552     1.699    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y97        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        7.285ns  (logic 4.300ns (59.023%)  route 2.985ns (40.977%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.646ns (routing 0.483ns, distribution 1.163ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           2.985     7.285    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X101Y311       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.646     3.047    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X101Y311       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.513ns  (logic 4.350ns (78.904%)  route 1.163ns (21.096%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.618ns (routing 0.483ns, distribution 1.135ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.115     5.415    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X100Y85        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.050     5.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.048     5.513    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X100Y85        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.618     3.019    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y85        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.422ns  (logic 4.337ns (79.992%)  route 1.085ns (20.008%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.608ns (routing 0.483ns, distribution 1.125ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.030     5.330    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X99Y88         LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.037     5.367 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.055     5.422    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X99Y88         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.608     3.009    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X99Y88         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.413ns  (logic 4.400ns (81.293%)  route 1.013ns (18.707%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.608ns (routing 0.483ns, distribution 1.125ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.958     5.258    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X99Y92         LUT4 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.100     5.358 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.055     5.413    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X99Y92         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.912     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.401 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.608     3.009    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X99Y92         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.015ns  (logic 0.505ns (49.761%)  route 0.510ns (50.239%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.141ns (routing 0.330ns, distribution 0.811ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.491     0.956    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X99Y92         LUT4 (Prop_E6LUT_SLICEM_I3_O)
                                                      0.040     0.996 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.019     1.015    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X99Y92         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.141     6.401    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X99Y92         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.049ns  (logic 0.479ns (45.682%)  route 0.570ns (54.318%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.140ns (routing 0.330ns, distribution 0.810ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.551     1.016    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X99Y88         LUT5 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.014     1.030 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.019     1.049    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X99Y88         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.140     6.400    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X99Y88         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.097ns  (logic 0.487ns (44.391%)  route 0.610ns (55.609%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.148ns (routing 0.330ns, distribution 0.818ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.594     1.059    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X100Y85        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.022     1.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.016     1.097    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X100Y85        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.148     6.408    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X100Y85        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.998ns  (logic 0.465ns (23.272%)  route 1.533ns (76.728%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.152ns (routing 0.330ns, distribution 0.822ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           1.533     1.998    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X101Y311       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.941     5.241    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.260 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X4Y3 (CLOCK_ROOT)    net (fo=478, routed)         1.152     6.412    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X101Y311       FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  sys_clk_ddr4_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.987ns  (logic 0.190ns (6.361%)  route 2.797ns (93.639%))
  Logic Levels:           2  (LUT3=2)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.038ns (routing 0.155ns, distribution 0.883ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLL_X0Y7             PLLE4_ADV                    0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                         net (fo=1, routed)           1.060     1.060    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock_i[0]
    SLICE_X81Y311        LUT3 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     1.150 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock__0/O
                         net (fo=1, routed)           0.935     2.085    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/pll_lock
    SLICE_X81Y323        LUT3 (Prop_A5LUT_SLICEL_I2_O)
                                                      0.100     2.185 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.802     2.987    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.038     1.953    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.248ns  (logic 0.098ns (7.852%)  route 1.150ns (92.148%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.031ns (routing 0.155ns, distribution 0.876ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.527     0.527    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y323        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.098     0.625 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.623     1.248    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X95Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.079     0.079    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.475     0.554 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.594    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.594 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.297     0.891    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.915 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          1.031     1.946    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.604ns  (logic 0.041ns (6.784%)  route 0.563ns (93.216%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.763ns (routing 0.108ns, distribution 0.655ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.269     0.269    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y323        LUT2 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.041     0.310 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.294     0.604    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X95Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.763     1.550    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X95Y319        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by sys_clk_ddr4_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.669ns  (logic 0.038ns (5.677%)  route 0.631ns (94.323%))
  Logic Levels:           1  (LUT3=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.770ns (routing 0.108ns, distribution 0.662ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y4            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.269     0.269    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X81Y323        LUT3 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.038     0.307 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.362     0.669    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock sys_clk_ddr4_clk_p rise edge)
                                                      0.000     0.000 r  
    J19                                               0.000     0.000 r  sys_clk_ddr4_clk_p (IN)
                         net (fo=0)                   0.100     0.100    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y131
                         DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.429     0.529 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.579    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    J19                  IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.579 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.189     0.768    d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in
    BUFGCE_X0Y138        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.787 r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/sys_clk_in_BUFGCE_collapsed_inst/O
    X4Y5 (CLOCK_ROOT)    net (fo=18, routed)          0.770     1.557    d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/lopt
    SLICE_X96Y320        FDRE                                         r  d_1_i/ddr4/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C





